ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 127

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ATmega1284PR231

Manufacturer Part Number
ATmega1284PR231
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega1284PR231

Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
10.2
8111C–MCU Wireless–09/09
Frame Transmit Procedure
A frame transmission comprises of two actions, a Frame Buffer write access and the transmis-
sion of the Frame Buffer content. Both actions can be run in parallel if required by critical
protocol timing.
Figure 10-2 on page 127
the frame consecutively. After a Frame Buffer write access, the frame transmission is initiated by
asserting pin 11 (SLP_TR) or writing command TX_START to register 0x02 (TRX_STATE),
while the radio transceiver is in state PLL_ON or TX_ARET_ON. The completion of the transac-
tion is indicated by interrupt IRQ_3 (TRX_END).
Figure 10-2. Transaction between AT86RF231 and Microcontroller during Transmit
Alternatively a frame transmission can be started first, followed by the Frame Buffer write access
(PSDU data); refer to
Initiating a transmission, either by asserting pin 11 (SLP_TR) or command TX_START to regis-
ter bits TRX_CMD (register 0x02, TRX_STATE), the radio transceiver starts transmitting the
SHR, which is internally generated.
This first phase requires 16 µs for PLL settling and 160 µs for SHR transmission. The PHR must
be available in the Frame Buffer before this time elapses. Furthermore the SPI data rate must be
higher than the PHY data rate selected by register bits OQPSK_DATA_RATE (register 0x0C,
TRX_CTRL_2) to ensure that no Frame Buffer under run occurs, indicated by IRQ_6 (TRX_UR),
refer to
Figure 10-3. Time Optimized Frame Transmit Procedure
Section 11.3 “High Data Rate Modes” on page
Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)
Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)
Figure 10-3 on page
Read IRQ_STATUS register, pin 24 (IRQ) deasserted
Read IRQ_STATUS register, pin 24 (IRQ) deasserted
illustrates the frame transmit procedure, when writing and transmitting
Write frame data (Frame Buffer access)
Write frame data (Frame Buffer access)
IRQ_3 (TRX_END) issued
IRQ_3 (TRX_END) issued
127. This is applicable for time critical applications.
137.
AT86RF231
127

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