ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 60

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

7.2.3.4
8111C–MCU Wireless–09/09
RX_AACK_NOCLK - RX_AACK_ON without CLKM
Table 7-11.
Note that this feature can be used in all scenarios, independent of other configurations. How-
ever, shorter acknowledgment timing is especially useful when using High Data Rate Modes to
increase battery lifetime and to improve the overall data throughput; refer to
Data Rate Modes” on page
If the AT86RF231 is listening for an incoming frame and the microcontroller is not running an
application, the microcontroller can be powered down to decrease the total system power con-
sumption. This special power-down scenario for systems running in clock synchronous mode
(see
state RX_AACK_ON_NOCLK. The radio transceiver functionality in this state is based on that in
state RX_AACK_ON with pin 17 (CLKM) disabled.
The RX_AACK_NOCLK state is entered from RX_AACK_ON by a rising edge at pin 11
(SLP_TR). The return to RX_AACK_ON state results either from a successful frame reception or
a falling edge on pin SLP_TR.
The CLKM pin is disabled 35 clock cycles after the rising edge at SLP_TR pin. This allows the
microcontroller to complete its power-down sequence. This is not valid for clock rates 250 kHz
and 62.5 kHz, where the main clock at pin 17 (CLKM) is switched off immediately.
In case of the reception of a valid frame, IRQ_3 (TRX_END) is issued and pin 17 (CLKM) is
turned on. A timing diagram is shown in
valid if it passes address filtering and has a correct FCS. If an ACK was requested the radio
transceiver enters BUSY_RX_AACK state and follows the procedure described in
“RX_AACK_ON - Receive with Automatic ACK” on page
After the transaction has been completed, the radio transceiver reenters the RX_AACK_ON
state.
The radio transceiver reenters the RX_AACK_ON_NOCLK state only, when the next rising edge
at SLP_TR pin occurs.
It is not recommended to operate the receiver in state RX_AACK_NOCLK with register bit
SLOTTED_OPERATION (register 0x2C, XAH_XTRL_0) set, refer to
Control Registers” on page
Register
Address
0x17
Section 6. “Microcontroller Interface” on page
Register
Overview of RX_AACK Configuration Bits
Bit
2
Register Name
AACK_ACK_TIME
68.
137.
Figure 6-16 on page
Description
0: Standard compliant acknowledgement timing
of 12 symbol periods. In slotted acknowledge-
ment operation mode, the acknowledgment
frame transmission can be triggered 6 symbol
periods after reception of the frame earliest.
1: Reduced acknowledgment timing of 2 symbol
periods (32 µs).
16) is supported by the AT86RF231 using the
51.
28. A received frame is considered
“Register Description -
AT86RF231
Section 11.3 “High
Section 7.2.3
60