ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 71

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

8111C–MCU Wireless–09/09
Bit
+0x04
Read/Write
Reset Value
Bit
+0x17
Read/Write
Reset Value
PA_EXT_EN
R/W
R/W
7
7
0
0
Reserved
IRQ_2_EXT_EN
6
R
0
R/W
6
0
Notes:
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating modes and
settings of the radio transceiver.
• Bit 7 - PA_EXT_EN
Refer to
• Bit 6 - IRQ_2_EXT_EN
Refer to
• Bit 5 - TX_AUTO_CRC_ON
If set, register bit TX_AUTO_CRC_ON enables the automatic FCS generation. For further
details refer to
• Bit 4 - RX_BL_CTRL
Refer to
• Bit [3:2] - SPI_CMD_MODE
Refer to
• Bit 1 - IRQ_MASK_MODE
Refer to
• Bit 0 - IRQ_POLARITY
Refer to
Register 0x17 (XAH_CTRL_1):
The XAH_CTRL_1 register is a control register for Extended Operating Mode.
• Bit [7:6] - Reserved
AACK_FLTR_RES_FT
TX_AUTO_CRC_ON
1. FORCE_PLL_ON is not valid for states SLEEP, P_ON, RESET, TRX_OFF, and all *_NOCLK
2. Using FORCE_PLL_ON to interrupt an TX_ARET transaction, it is recommended to check
Section 11.5 “RX/TX Indicator” on page
Section 11.6 “RX Frame Time Stamping” on page
Section 11.7 “Frame Buffer Empty Indicator” on page
Section 6.3 “Radio Transceiver Status information” on page
Section 6.6 “Interrupt Logic” on page
Section 6.6 “Interrupt Logic” on page
R/W
5
0
states, as well as STATE_TRANSITION_IN_PROGRESS towards these states.
register bits [7:5] of register address 0x32 for value 0. If this value is different, TRX_CMD
sequence FORCE_TRX_OFF shall be used immediately followed by TRX_CMD sequence
PLL_ON. This performs a state transition to PLL_ON.
R/W
5
1
Section 8.2 “Frame Check Sequence (FCS)” on page
AACK_UPLD_RES_FT
RX_BL_CTRL
R/W
4
0
R/W
4
0
R/W
3
Reserved
0
SPI_CMD_MODE
3
R
0
29.
29.
AACK_ACK_TIME
147.
R/W
2
0
R/W
2
0
150.
IRQ_MASK_MODE
AACK_PROM_MODE
152.
R/W
1
0
R/W
1
0
24.
85.
IRQ_POLARITY
AT86RF231
Reserved
R/W
0
0
0
R
0
TRX_CTRL_1
XAH_CTRL_1
71