ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 128

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

11. AT86RF231 Extended Feature Set
11.1
11.1.1
11.1.2
8111C–MCU Wireless–09/09
Security Module (AES)
Overview
Security Module Preparation
The security module (AES) is characterized by:
The security module is based on an AES-128 core according to FIPS197 standard, refer to [5].
The security module works independent of other building blocks of the AT86RF231, encryption
and decryption can be performed in parallel to a frame transmission or reception.
Controlling the security block is implemented as an SRAM access to address space 0x82 to
0x94. A Fast SRAM access mode allows simultaneously writing new data and reading data from
previously processed data within the same SPI transfer. This access procedure is used to
reduce the turnaround time for ECB mode, see
Access” on page
In addition, the security module contains another 128-bit register to store the initial key used for
security operations. This initial key is not modified by the security module.
The use of the security module requires a configuration of the security engine before starting a
security operation. The following steps are required:
Table 11-1.
Before starting any security operation a key must be written to the security engine, refer to
tion 11.1.3 “Security Key Setup” on page
AES engine KEY mode using register bits AES_MODE (SRAM address 0x83, AES_CTRL).
The following step selects the AES mode, either electronic code book (ECB) or cipher block
chaining (CBC). These modes are explained more in detail in sections
Operation Modes” on page
bit AES_DIR (SRAM address 0x83, AES_CTRL).
As next the 128-bit plain text or ciphertext data has to be provided to the AES hardware engine.
The data uses the SRAM address range 0x84 - 0x93.
Step
• Hardware accelerated encryption and decryption
• Compatible with AES-128 standard (128-bit key and data block size)
• ECB (encryption/decryption) mode and CBC (encryption) mode support
• Stand-alone operation, independent of other blocks
1
2
3
4
5
Description
Key Setup
AES Mode
Write Data
Start Operation
Read Data
AES Engine Configuration Steps
132.
Description
Write encryption or decryption key to SRAM
Select AES mode: ECB or CBC
Select encryption or decryption
Write plaintext or cipher text to SRAM
Start AES operation
Read cipher text or plaintext from SRAM
129. Further, encryption or decryption must be selected with register
129. The key set up requires the configuration of the
Section 11.1.5 “Data Transfer - Fast SRAM
Section 11.1.4 “Security
AT86RF231
Section
Section 11.1.3
Section 11.1.4.1
Section 11.1.4.2
Section 11.1.5
Section 11.1.5
Sec-
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