RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 103

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
4.3.6 Segmentation Internal SRAM Memory Map
Table 4-22. Segmentation Internal SRAM Memory Map
28234-DSH-001-B
0x1400-0x1407
0x1408-0x140F
0x14F8-0x14FF
0x1500-0x1507
0x1508-0x150F
0x15F8-0x15FF
0x1600-0x17FF
Address
Segmentation Status Queue Base Table Registers (SEG_SQ_QUn):
Internal Transmit Queue Base Table Registers (SEG_TQ_QUn):
Further Internal Segmentation and Scheduler Registers:
SEG_SQ_QU0
SEG_SQ_QU1
SEG_SQ_QU31
SEG_TQ_QU0
SEG_TQ_QU1
SEG_TQ_QU31
Reserved
Name
As indicated in
range 0x1400-0x17FF.
address range 0x1400-0x14FF.
address range 0x1500-0x15FF.
0x1600-0x17FF.
The segmentation status queue base table registers (SEG_ST_QUn) are in the
The internal transmit queue base table registers (SEG_TQ_QUn) are in the
Other internal segmentation and scheduler registers are in the address range
Mindspeed Technologies
Status Queue 0 Base Table
Status Queue 1 Base Table
Status Queue 31 Base Table
Transmit Queue 0 Base Table
Transmit Queue 1Base Table
Transmit Queue 31Base Table
Not Implemented
Table
4-22, the segmentation internal SRAM is in the address
™
4.3 Segmentation Control and Data Structures
Description
4.0 Segmentation Coprocessor
4-25