RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 301

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
0xf8 - Reassembly Free Buffer Queue Base Register (RSM_FQBASE)
This register determines the base address of both banks of contiguous free buffer queue spaces. The base
address is a 16-bit number. Since both banks reside in SAR shared memory (23-bits of byte addressing), the
structures can start on 128 byte boundaries. Bank 0 has additional boundary requirements if the buffer return
mechanism is enabled.
28234-DSH-001-B
31-16
15-0
9-5
4-0
Bit
Bit
10
Field
Field
Size
Size
16
16
1
5
5
OAM_QU_EN
OAM_BFR_QU
OAM_STAT_QU
FBQ1_BASE
FBQ0_BASE
Name
Name
Mindspeed Technologies
OAM Buffer/Status Queue Enable. When a logic high, an OAM cell will use
the global OAM free buffer queue and status queue instead of per-channel
resources.
OAM Free Buffer Queue. When OAM_QU_EN is a logic high, OAM cells will
use buffers from the free buffer queue identified by OAM_BFR_QU.
OAM Status Queue. When OAM_QU_EN is a logic high, OAM cells will post
status to the status queue identified by OAM_STAT_QU.
Free Buffer Queue Bank 1 base address.
Free Buffer Queue Bank 0 base address.
™
Description
Description
13.5 Reassembly Registers
13.0 RS8234 Registers
13-19