RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 282

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

12.0 ATM Utopia Interface
12.9 Transmit Cell Synchronization Logic
12-12
12.9 Transmit Cell Synchronization Logic
The transmit cell synchronization logic copies cell data from the transmit cell
FIFO to the transmit ATM physical interface while performing the following
functions:
to the transmit ATM physical interface unit, with cell delineation pulses at the
starting byte of every cell. Only complete 53-byte cells are supplied to the ATM
physical interface. If the transmit cell FIFO is empty, the transmit cell
synchronization logic indicates that no more data can be transferred to the framer.
• Reads 32-bit words from the transmit cell FIFO and converts them to a
• Maintains a sequence counter that delineates the various components of
• Inserts a blank (all-zero) HEC byte, used as a placeholder, into the
• Generates appropriate cell delineation pulses to the transmit ATM physical
• If the ATM physical transmit interface runs out of cells to transmit, the
The transmit cell synchronization logic supplies a continuous stream of octets
stream of octets, with the MSB of each 32-bit word corresponding to the
first byte derived from that word (big-endian format).
each ATM cell (4-byte header, 48-byte payload) in the outgoing byte
stream.
outgoing byte stream representing each ATM cell. The HEC placeholder is
inserted after the first four bytes (the ATM header) have been transferred.
interface logic, for use in generating the TXSOC output, and also in
verifying synchronization with the framer device.
device sets the SEG_UNFL bit in the HOST_ISTAT0/LP_ISTAT0
registers.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234