RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 121

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
5.3.5 BOM Synchronization Signal
28234-DSH-001-B
The STAT[1:0] output pins can be programmed to provide an indication that a
BOM cell is being written across the PCI bus. Additional external circuitry could
snoop the BOM cell for a service level protocol header, and perform appropriate
lookup as the CPCS-PDU is being reassembled. To configure the STAT pins, set
the STATMODE field in the CONFIG0 register to 0x00. The STAT output truth
table illustrated in
Table 5-2. STAT Output Pin Values for BOM Synchronization
External circuitry would detect a BOM cell transfer by detecting a logic high on
either STAT pin during a SAR PCI master write address cycle. External circuitry
can then snoop the subsequent data cycles of the BOM cell transfer to extract the
appropriate protocol overhead.
NOT BOM
AAL5 BOM
AAL0 BOM
NOT USED
The STAT output pins are valid during a SAR PCI master write address cycle.
Mindspeed Technologies
Table
5-2.
STAT[1]
0
0
1
1
™
5.0 Reassembly Coprocessor
5.3 CPCS-PDU Processing
STAT[0]
0
1
0
1
5-17