RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 331

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
14.3.1 Reassembly Control Registers
28234-DSH-001-B
Table 14-6. Table of Values for Reassembly Control Register Initialization (1 of 2)
RSM_CTRL0
(Reassembly Control
Register 0)
RSM_CTRL1
(Reassembly Control
Register 1)
RSM_FQBASE
(RSM Free Buffer
Queue Base Register)
Register
RSM_ENABLE
RSM_RESET
VPI_MASK
RSM_PHALT
FWALL_EN
RSM_FBQ_DIS
RSM_STAT_DIS
GTO_EN
MAX_LEN
GDPRI
Rsvd
OAM_FF_DSC
OAM_EN
OAM_QU_EN
OAM_BFR_QU
OAM_STAT_QU
Rsvd
FBQ1_BASE
FBQ0_BASE
14.3 Reassembly Initialization
Before reassembly is enabled, the host must allocate and initialize all of the
reassembly control registers.
Field
Mindspeed Technologies
Initialized
Value
0xB0
0x10
0x30
0-1
0x4
0x0
0x4
0x4
0x0
0
1
0
1
0
0
1
1
1
1
Table 14-6
Must be set to a logic low until initialization of all
reassembly structures is complete. Set to a logic high
to commence reassembly process.
Use CONFIG0(GLOBAL_RESET) to initialize the SAR.
UNI VPI space selected.
RSM halt on receive parity error disabled.
Firewall function enabled.
Free buffer queue underflow protection enabled.
Status queue overflow protection enabled.
Enable internal time-out interrupt.
AAL5 max CPCS-PDU length = 16,384 bytes.
Global Service Discard Priority = 4.
Must be initialized to zero.
OAM cells discarded when Incoming DMA FIFO
almost full.
OAM detection enabled.
Global OAM FB and Stat queues enabled.
Global OAM free buffer queue = 4.
Global OAM status queue = 4.
Must be initialized to zero.
Free buffer queue bank 1 starts at 0x5800 in SAR
shared memory.
Free buffer queue bank 0 starts at 0x1800 in SAR
shared memory.
lists the initial value(s) for each field.
™
14.0 SAR Initialization - Example Tables
Notes
14.3 Reassembly Initialization
14-9