RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 136

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

5.0 Reassembly Coprocessor
5.6 Status Queue Operation
5.6.1 Structure
Figure 5-14. Data Structure Locations for Status Queues
5-32
5.6 Status Queue Operation
The RS8234 reports reassembly status to the host via the reassembly status queue.
The reassembly coprocessor normally writes a status queue entry when a
complete CPCS-PDU has been reassembled. One field of the status queue entry
(BD_PNTR) points to the first buffer descriptor in the linked list of buffer
descriptors for that reassembled PDU, and the rest of the fields of that status
queue entry provide data on the status of the reassembled PDU, then used by the
host in directing further processing.
Two data structures are maintained as illustrated in
memory and one in SAR shared memory. The status queues (HSTAT_QU) reside
in host memory, and the status queue base table resides in SAR shared memory,
and allows for up to 32 independent circular status queues.
status queue base table contains status queue base information for up to 32
queues. The queues are accessed via a status pool number, the STAT field in the
RSM VCC Table. This field is used as an index to the correct status queue base
table entry.
address of the status queue associated with that status queue base table entry. The
WRITE field is the index pointer maintained by the RS8234, incremented each
time a status queue entry is written, to point to the next status queue entry for that
status queue.
The status queue base table is located at 0x001000 in internal SRAM. The
The BASE_PNTR field in the status queue base table entry, points to the base
HOST
Mindspeed Technologies
Status Queue Base Table
(Internal in the RS8234)
ATM ServiceSAR Plus with xBR Traffic Management
SAR-Shared
™
Figure
5-14: one in host
28234-DSH-001-B
RS8234
100074_035