RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 278

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

12.0 ATM Utopia Interface
12.6 Slave UTOPIA Mode
Figure 12-5. Receive Timing in Slave UTOPIA Mode
12-8
RXD/TXPAR
NOTE(S):
(1)
(2)
(3)
FRCTRL
RXCLAV
RXSOC
RxClav goes inactive when there is room in the receive FIFO buffer for a complete cell.
RxClav goes active when there is no longer room in the receive FIFO buffer for another complete cell.
RxEN* need not be inactive when RxClav is active.
RXEN*
(1)
H1
12.6 Slave UTOPIA Mode
The slave UTOPIA mode is similar to the UTOPIA mode, except the direction of
the enable signals and FIFO flags are reversed. This allows a switch fabric or
backplane to directly control the physical port. The transmit and receive enable
signals are generated by the physical layer instead of the RS8234. The TxFull*
signal is changed to the TxEmpty* signal and is an output of the RS8234. The
RxEmpty* signal is changed to the RxFull* signal, and is also an output of the
RS8234. This mode supports only a cell-level handshake protocol.
edge of FRCTRL when RXEN* is active (see
computed over the RXD[7:0] lines is compared to the RXPAR input. If there is a
parity error, the FR_PAR_ERR bit is set in the HOST_ISTAT0/LP_ISTAT0
registers. No data is discarded upon a parity error unless the RSM_PHALT bit in
the RSM_CTRL Register is set to a logic high. If so, the reassembly coprocessor
halts upon a parity error. The RXSOC signals to the RS8234 the start of cell. The
RXCLAV output is the receive FIFO full signal. When it is active, the RS8234
cannot accept another cell. The RS8234 sets RXCLAV inactive when it has room
in the receive FIFO for another cell. The physical device sets RXEN* to a logic
low if it can transfer an octet. The FR_RMODE bit in the CONFIG0 Register
should be set to a logic low in this mode.
H2
Received data is latched from the RXD[7:0] and RXPAR lines on the rising
X
Mindspeed Technologies
H3
***
P44
ATM ServiceSAR Plus with xBR Traffic Management
P45
P46
™
(2)
P47
Figure
P48
12-5). The 8-bit odd parity
X
(3)
28234-DSH-001-B
X
H1
RS8234
100074_084
H2