RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 287

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
0x0c - System Status Register (SYS_STAT)
The System Status Register provides read-only system status. This register reflects the device ID and version
information for the part, as well as pin programmable options that otherwise might not be visible to the
processors. It also contains expanded information for the status located in the HOST_ISTAT0 and LP_ISTAT0
registers.
0x14 - Configuration Register 0 (CONFIG0)
This register provides all of the control and configuration bits that are not associated with the reassembly and
segmentation coprocessors. The majority of these bits are configuration (which occurs at initialization time) and
are not changed dynamically. The assertion of the HRST* system reset pin will clear all of the bits in the
CONFIG0 register except for MEMCTRL, which will be set high.
28234-DSH-001-B
31–17
16–12
27–26
9, 8
7–4
3–0
Bit
11
10
Bit
31
30
29
28
Field
Size
15
Field
Size
5
1
1
2
4
4
1
1
1
1
2
Reserved
PCI_BUS_STATUS
[4:0]
RAMMODE
PROCMODE
FRCFG[1:0]
VERSION [3:0]
DEVICE[3:0]
LP_ENABLE
GLOBAL_RESET
PCI_MSTR_RESET
PCI_ERR_RESET
Reserved
Name
Name
Mindspeed Technologies
Not implemented at this time.
The status bits are as follows:
4 = Target Abort
3 = Master Abort
2 = Parity Error
1 = Interface Disabled
0 = Internal Failure
Reflects corresponding error bits in the PCI Configuration register. Bits are
reset by either a write to the PCI Configuration register by the host, or by
setting CONFIG0 (PCI_ERR_RESET) bit.
Reflects the state of the RAMMODE input pin.
Reflects the state of the PROCMODE input pin.
Reflects the state of the FRCFG[1:0] input pins.
Version number for the RS8234; for Rev A set to zero, for Rev B set to one,
for Rev C set to two, for Rev D set to three, for Rev E set to four, and for Rev
F set to five.
Device ID for the RS8234; set to two.
When set, this bit causes the PRST* output pin to be high. This can be
used to reset the local processor.
When set, this bit causes reset of the segmentation and reassembly
coprocessors as well as all latched status.
When set, this bit resets the PCI master logic. Once active, this bit must
stay active for 16 cycles of the HCLK input signal.
When set, resets all PCI error bits in the PCI configuration, including RMA,
RTA, DPR, INTF_DIS, INT_FAIL, and MERROR. This also re-enables PCI
master operation.
Always set to zero.
™
Description
Description
13.0 RS8234 Registers
13.2 System Registers
13-5