RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 279

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Figure 12-6. Transmit Timing in Slave UTOPIA Mode
28234-DSH-001-B
TXD/TXPAR
NOTE(S):
(1)
(2)
(3)
(4)
FRCTRL
TXCLAV
TXSOC
TXEN*
TXCLAV goes active when a complete cell is in the transmit FIFO buffer.
Example of physical device deactivating TXEN*.
The TXD/TXPAR and TXSOC lines are three-stated (floated) when TXEN* is sampled high (de-asserted).
Physical device can keep TXEN* active while TXCLAV is inactive.
(1)
H1
TXEN* is sampled asserted. Simultaneously, the 8-bit odd parity computed over
the TXD[7:0] lines is driven on to the TXPAR output. The TXSOC line is driven
by the SAR to indicate start of cell. If the TXCLAV output is asserted by the
RS8234, the transmit FIFO does not contain a complete cell. (See
Transmit data is driven on TXD[7:0] on the rising edge of FRCTRL after
***
Mindspeed Technologies
H5
P1
P2
(2)
(3)
(3)
P3
™
***
P48
(4)
12.0 ATM Utopia Interface
12.6 Slave UTOPIA Mode
H1
Figure
H2
12-2.)
8234_006
12-9