RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 291

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
0x84 - Segmentation VCC Table and Schedule Table Base Address Register
(SEG_VBASE)
The SEG_VBASE register sets the base address in SAR shared memory for the segmentation VCC table and the
schedule table. Both base addresses are 128-byte aligned and only the 16 most significant bits of the address are
specified in the SEG_VBASE register.
0x88 - Segmentation PM Base Register (SEG_PMBASE)
The SEG_PMBASE register sets the base address in SAR shared memory for the VBR bucket table and the
performance monitoring table. Both base addresses are 128-byte aligned and only the 16 most significant bits of
the address are specified in the SEG_PMBASE register.
28234-DSH-001-B
31-16
31-16
15-0
15-0
1-0
Bit
Bit
Bit
3
2
Field
Field
Field
Size
Size
Size
16
16
16
16
1
1
2
SEG_HS_DIS
TX_RND
TR_SIZE[1:0]
SEG_SCHB[15:0]
SEG_VCCB[15:0]
SEG_BCKB[15:0]
SEG_PMB[15:0]
Name
Name
Name
Mindspeed Technologies
Base address for the schedule table.
Base address for the segmentation VCC table.
Base address for the VBR bucket table. (See
loading bucket table entries.)
Base address for the performance monitoring table.
Segmentation Host Status Disable—Disable segmentation check for PCI
memory status queue full condition. If this bit is not set, the segmentation
coprocessor will not segment any cells for a VCC assigned to a full PCI
memory status queue. This bit can be used to disable overflow checking
when the queues are sized large enough to prevent overflow.
Set for transmit queue servicing in round-robin order.
Clear for transmit queue servicing in priority order (31 is highest priority).
Number of entries in each transmit queue.
00 = 64
01 = 256
10 = 1,024
11 = 4,096
™
Description
Description
Description
Section
13.3 Segmentation Registers
13.0 RS8234 Registers
6.2.4, for details on
13-9