RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 280

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

12.0 ATM Utopia Interface
12.7 Loopback Mode
Figure 12-7. Source Loopback Mode Diagram
12-10
SYSCLK
12.7 Loopback Mode
The physical interface can be internally looped by setting the FR_LOOP bit in the
CONFIG0 Register to a logic high. This mode uses the internal system clock for
operation; therefore, a framer clock is not needed during loopback operation.
data and control signals, so the path from the segmentation coprocessor to the
reassembly coprocessor can be tested. The internal connections of the PHY
device interface signals are connected, as
side is put into the UTOPIA Mode and the receive side is put into the Reverse
UTOPIA Mode.
three-stated, so there are no output conflicts with other devices connected to these
signals.
NOTE:
When the signal “fr_src_loop” equals one, the interface will loop back the
In this mode, the outputs of the chip, txd, txpar, txsoc, txen_, and rxclav_ are
Transmit
UTOPIA
Receive
Reverse
UTOPIA
Side in
Side In
A reset of the reassembly coprocessor is required after the changing of the
FR_LOOP bit, because this changes the source of the clock to the physical
interface circuitry. To accomplish this reset, assert RSM_CTRL0
(RSM_RESET).
Mode
Mode
Mindspeed Technologies
RXD[15:0]
TXD[15:0]
RXCLAV
TXCLAV
RXSOC
TXSOC
RXPAR
TXPAR
RXEN_
TXEN_
ATM ServiceSAR Plus with xBR Traffic Management
™
Figure 12-7
illustrates. The transmit
28234-DSH-001-B
RS8234
100074_086