RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 268

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

11.0 PCI Bus Interface
11.9 Interface Module to Serial EEPROM
11.9.1 EEPROM Format
Table 11-1. EEPROM Fields
11-8
0x00
0x01-0x03
0x04-0x05
0x06-0x07
0x08
0x09
0x0a
NOTE(S):
(1)
Address
System BIOS is typically responsible for setting these bits after programming the PCI Base address register.
Offset
FIELD_ENABLES
Reserved
SVID
SID
General Enables
Latency Timer
Memory Size Mask
Name
11.9 Interface Module to Serial EEPROM
The Interface Module implements the protocol to allow the PCI core to connect to
a serial EEPROM.
The first 32 bytes of the 128-byte EEPROM are used to store PCI configuration
information, loaded into the PCI Configuration space at reset. Unless otherwise
specified, all unused bytes are reserved and should be programmed to 0x00. Bytes
above address offset 0x20 can be used by application software or device drivers as
needed. The EEPROM fields are described in
Mindspeed Technologies
Bit 5: Load Memory Size Mask from EEPROM.
Bit 4: Load Latency Timer from EEPROM.
Bit 3: Load General Enables from EEPROM.
Bit 2: Disable Capability Registers (for Power Management).
Bit 1: Load Subsystem ID (SID) from EEPROM.
Bit 0: Load Subsystem Vendor ID (SVID) from EEPROM.
Set to zeros.
Subsystem Vendor ID.
Subsystem ID.
Bit 4: Special Status Register Bit 29 (SLAVE_SWAP, Slave Control Byte Swap).
Bit 3: Special Status Register Bit 30 (MSTR_CTRL_SWAP, Master Control Byte
Swap).
Bit 2: PCI Command Register Bit 6 (PE_EN, Enable Detection of Parity Errors).
Bit 1: PCI Command Register Bit 2 (M_EN, Master Enable).
Bit 0: PCI Command Register Bit 1 (MS_EN, Memory Space Enable).
Master Latency Timer
Valid Mask Values:
Bit 7 6 5 4 3 2 1 0 = Size
x 0 0 0 0 0 0 0 = 8 M
ATM ServiceSAR Plus with xBR Traffic Management
™
Description
Table
11-1.
(1)
28234-DSH-001-B
(1)
RS8234