RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 315

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
This register contains the interrupt enables that correspond to the statuses in the LP_ISTAT1 register. The
assertion of the HRST* system reset pin will clear all of the LP_IMASK1 interrupt enables.
28234-DSH-001-B
0x1f4 - Local Processor Interrupt Mask Register 1 (LP_IMASK1)
30-27
23-16
9-3
Bit
31
26
25
24
15
14
13
12
11
10
2
1
0
Field
Size
1
4
1
1
1
8
1
1
1
1
1
1
7
1
1
1
EN_PCI_BUS_ERROR
Reserved
EN_DMA_AFULL
EN_FR_PAR_ERR
EN_FR_SYNC_ERR
Reserved
EN_RSQUEUE_FULL
EN_RSM_OVFL
EN_RSM_HS_FULL
EN_RSM_LS_FULL
EN_RSM_HS_EMPT
EN_RSM_LS_EMPT
Reserved
EN_SEG_UNFL
EN_SEG_HS_FULL
EN_SEG_LS_FULL
Name
Mindspeed Technologies
Enables an interrupt when PCI_BUS_ERROR status is a logic 1.
Set to zero.
Enables an interrupt when DMA_AFULL status is a logic 1.
Enables an interrupt when FR_PAR_ERR status is a logic 1.
Enables an interrupt when FR_SYNC_ERR status is a logic 1.
Set to zero.
Enables an interrupt when RSQUQUQ_FULL status is a logic 1.
Enables an interrupt when RSM_OVFL status is a logic 1.
Enables an interrupt when RSM_HS_FULL status is a logic high.
Enables an interrupt when RSM_LS_FULL status is a logic high.
Enables an interrupt when RSM_HS_EMPT status is a logic high.
Enables an interrupt when RSM_LS_EMPT status is a logic high.
Set to zero.
Enables an interrupt when SEG_UNFL status is a logic high.
Enables an interrupt when SEG_HS_FULL status is a logic high.
Enables an interrupt when SEG_LS_FULL status is a logic high.
™
Description
13.6 Counters and Status Registers
13.0 RS8234 Registers
13-33