RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 245

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Table 10-1. Processor Interface Pins
28234-DSH-001-B
PROCMODE
PCS*
PAS*
PWNR
PADDR[1:0]
PBSEL[1:0]
PBE[3:0]*
PWAIT*
PBLAST*
PRDY*
PFAIL*
(1)
(2)
(3)
Direction given with respect to the RS8234.
This output corresponds to the READY* or RDYRCV* input in the i960 architecture.
The processor system is responsible for controlling the direction of the bidirectional data bus transceiver. In the i960
architecture, this can be controlled by the DT/R* signal.
Signal
Dir
O
I
I
I
I
I
I
I
I
I
I
(1)
Processor interface mode select input—A logic low on this input enables the local processor mode
of operation.
Processor interface chip select—A logic low on this signal in conjunction with a logic low on PAS*
at the rising edge of SYSCLK initiates a memory request to the memory controller.
Processor address strobe— A logic low on this signal in conjunction with a logic low on PCS*
latches the value of PWNR, PBSEL[1:0], PADDR[1:0], and PBE[3:0]* at the rising edge of SYSCLK.
Processor write/read select—A logic one on this input indicates a write cycle, a logic zero indicates
a read cycle. Latched at rising edge of SYSCLK when PAS* and PCS* are active.
Word select address inputs—Indicates the word address for a single cycle access, or the first word
for a multi-cycle burst access. Latched at rising edge of SYSCLK when PAS* and PCS* are active.
Bank select inputs—Decode to select MCS[3:0]*. Latched at rising edge of SYSCLK when PAS*
and PCS* are active.
Byte select inputs—Active low. Allows individual bytes of selected word to be written. Not active on
reads. Latched at rising edge of SYSCLK when PAS* and PCS* active. PBE[3]* controls writes to
LDATA[31:24]; PBE[2]* controls LDATA[23:16]; etc.
Processor wait input—Allows the processor to insert a variable number of wait states to extend
memory transaction. Must be active on rising edge of SYSCLK with PRDY* active to insert wait
cycle. Can be used to interface to half speed or slow processor bus or to allow the use of slow
transceivers. If insertion of wait states is not required, set this input to a logic high. This signal can
only be active, logic low, when PBLAST* is a logic high.
Processor burst last input—Indicates the last word of a cycle. Must be active on rising edge of
SYSCLK with PRDY* active to indicate last cycle. If burst accesses and wait cycles generated by
PWAIT* are not required, this signal should be set to a logic low.
Processor interface ready signal—A logic low on this signal at rising edge of SYSCLK indicates
that the present cycle has been completed. If a read cycle, the data is valid to latch by the
processor; if a write cycle, the data has been written and can be removed from the bus. When
PRDY* is active, wait states can be inserted with PWAIT*, or a single or burst cycle can be
terminated by PBLAST*
The local processor can indicate a failure of its internal self-test or initialization processes by
asserting the PFAIL* input to the RS8234.
10.2 Interface Pin Descriptions
The local processor bus interface consists of the control, address, and status
signals described in
i80960CA/CF interface description, for further information on these interface
pins.
Mindspeed Technologies
(2)
.
Table
10-1. Refer to
Description
™
Table 2-1
and
10.0 Local Processor Interface
10.2 Interface Pin Descriptions
Figure
10-7,
10-3