RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 311

• Manufacturer Part Number: RS8234
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Local Processor Interrupt Status Registers
The Local Processor Interrupt Status Registers contain all the interruptible status bits for the local processor.
The corresponding interrupt enables are located in the LP_IMASKx registers. Status types are defined as:
28234-DSH-001-B
0x1e0 - Local Processor Interrupt Status Register 0 (LP_ISTAT0)
L
E
DE
NOTE:
25-24
21-19
14-12
Bit
31
30
29
28
27
26
23
22
18
17
16
15
Level sensitive status—A logic one on the status bit will cause an interrupt when enabled by the
corresponding IMASK bit. Reading the status does not clear the status or interrupt. The source of
the condition causing the status must be cleared before the status or interrupt is cleared.
Event driven status—A 0 -> 1 transition on the status bit causes an interrupt when enabled.
Reading the status register clears the status bit and the interrupt.
Dual event status—A 0 -> 1 and 1 -> 0 transition on the status bit can be enabled to cause an
interrupt. Reading the status register clears the status bit and the interrupt.
Only local processor reads will reset the status bits in the LP_ISTAT0 register.
Field
Size
1
1
1
1
1
1
2
1
1
3
1
1
1
1
3
Type
—
—
—
—
—
—
E
E
E
E
L
E
L
L
E
RTC_OVFL
ALARM1
Reserved
LP_MBOX_WRITTEN
HOST_MBOX_READ
Reserved
Reserved
Reserved
LSTAT1
Reserved
GFC_LINK
RSM_RUN
RSM_HS_WRITE
RSM_LS_WRITE
Reserved
Mindspeed Technologies
Name
Clock register overflow.
Set when ALARM1 register matches CLOCK register.
Read as zero.
This bit is set upon a write to the LP_MBOX register by
the host processor.
This bit is set upon the read of the HOST_MBOX register
by the host processor.
Read as zero.
Read as zero.
Read as zero. Reserved for future status page
expansion.
This bit is set when any bit in LP_ISTAT1 is set.
Read as zero.
Set when three consecutive received cells have GCF
SET_A, SET_B, or HALT bits set.
Set when the reassembly machine is running. Will be
high when the RSM coprocessor is processing a cell.
Indicates reassembly host status has been written by
the RS8234 to status queues 0 through 15. For queue
number, read HOST_ST_WR which must be read in
order to clear status bit.
Indicates that a reassembly local status queue has been
written by the RS8234.
Read as zero.
™
13.6 Counters and Status Registers
Description
13.0 RS8234 Registers
13-29