tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 147

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.6.4.4
INTCLR
request being suspended. Do not clear an interrupt request before reading the IVR value. When an interrupt request is
cleared, the IVR value is also cleared and the interrupt factor cannot be determined anymore.
(Note 1) This register must be 16-bit accessed.
(Note 2) In order to maintain interrupt factors regardless of the active state setting of INTC IMCx
(Note 3) Bit manipulation instructions cannot be used to access this register.
(Note 4) External transfer requests due to DMAC interrupt factors are not cleared. Once an
Setting the IVR [8:0] for the corresponding interrupt factor into the INTCLR register enables to clear any interrupt
Interrupt Request Clear Registers (INTCLR)
<EIMxx>, clear the interrupt request in any case whether in “H” level, “L” level, rising
edge, or falling edge.
external transfer request is accepted, it will not be canceled until the DMA transfer is
executed. Therefore, any unnecessary external transfer request should be cleared by
executing DMA transfer, by disabling interrupts using IMCx <ILxxx> or by canceling the
corresponding DMAC activation factors using IMCx<DMxx> before accepting such
external transfer requests.
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
EICLR7
Set the IVR <IVR8:0> value that corresponds to the interrupt request that you would like to clear.
15
23
31
7
0
IVR <IVR8:0> value setting to clear the interrupt request
EICLR6
TMP19A44(rev1.3) 6-97
14
22
30
6
0
EICLR5
13
21
29
5
0
“0” is read.
EICLR4
12
20
28
R
0
4
0
“0” is read.
“0” is read.
R/W
R
R
0
0
EICLR3
11
19
27
3
0
EICLR2
10
18
26
2
0
TMP19A44
EICLR1
17
25
1
9
0
2010-04-01
request that
like to clear.
Set the IVR
correspond
you would
value that
<IVR8:0>
interrupt
s to the
EICLR0
EICLR8
R/W
16
24
0
0
8
0