tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 308

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

16-bit Timer/Event Counters (TMRBs)
11.3.4
11.3.5
11.3.6
11.3.7
These are 16-bit registers for latching values from the UC0 up-counter.
This is a circuit that controls the timing of latching values from the UC0 up-counter into the TB0CP0
and TB0CP1 capture registers.
<TB0CPM1:0>.
Software can also be used to import values from the UC0 up-counter into the capture register;
specifically, UC0 values are taken into the TB0CP0 capture register each time "0" is written to
TB0MOD<TB0CP0>. To use this capability, the prescaler must be running (TB0RUN<TB0PRUN> =
"1").
These are 16-bit comparators for detecting a match by comparing set values of the UC0 up-counter with
set values of the TB0RG0 and TB0RG1 timer registers. If a match is detected, INTTB0 is generated.
The timer flip-flop (TB0FF0) is reversed by a match signal from the comparator and a latch signal to
the capture registers. It can be enabled or disabled to reverse by setting the TB0FFCR<TB0C1T1,
TB0C0T1, TB0E1T1, TB0E0T1>.
The value of TB0FF0 becomes undefined after a reset. The flip-flop can be reversed by writing "00" to
TB0FFCR<TB0FF0C1:0>. It can be set to "1" by writing "01," and can be cleared to "0" by writing
"10."
The value of TB0FF0 can be output to the timer output pin, TB0OUT (shared with P54). To enable
timer output, the port 5 related registers P5CR and P5FC must be programmed beforehand.
Capture Registers (TB0CP0, TB0CP1)
Capture
Comparators (CP0, CP1)
Timer Flip-flop (TB0FF0)
TMP19A44(rev1.3) 11-10
The timing with which to latch data is specified by TB0MOD
TMP19A44
2010-04-01