tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 439

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Bus Interface (SBI)
Master
16.5.11 Slave Address Match Detection Monitor
16.5.12 General-call Detection Monitor
16.5.13 Last Received Bit Monitor
Master
A
A master compares the SDA bus line level and the internal SDA output level at the rising of the SCL
line. If there is a difference between these two values, the master loses arbitration and sets SBI0SR
<AL> to "1."
When <AL> is set to "1," SBISR <MST, TRX> are cleared to "0," causing the SBI to operate as a slave
receiver. <AL> is cleared to "0" when data is written to or read from SBIDBR or data is written to
SBICR2.
B
When the SBI operates as a slave device in the address recognition mode (I2CCR <ALS> = "0"),
SBISR <AAS> is set to "1" on receiving the general-call address or the slave address that matches the
value specified at I2CCR. When <ALS> is "1," <AAS> is set to "1" when the first data word has been
received. <AAS> is cleared to "0" when data is written to or read from SBIDBR.
When the SBI operates as a slave device, SBISR <AD0> is set to "1" when it receives the general-call
address; i.e., the eight bits following the start condition are all zeros. <AD0> is cleared to "0" when the
start or stop condition is detected on the bus.
SBISR <LRB> is set to the SDA line value that was read at the rising of the SCL line. In the
acknowledgment mode, reading SBISR <LRB> immediately after generation of the INTS0 interrupt
request causes ACK signal to be read.
Fig. 16.8 Example of Master B Losing Arbitration (D7A = D7B, D6A = D6B)
Internal SCLoutput
Internal SDA
output
Internal SCL output
Internal SDA
output
Access to SBIDBR or
SBICR2
<AL>
<MST>
<TRX>
D7A
D7B
1
1
TMP19A44 (rev1.3) 16-15
D6A
D6B
2
2
D5A
3
3
Internal SDA output is held high
because Master B has lost arbitraiton.
D4A
4
4
D3A
5
Clock output stops here
D2A
6
D1A
7
D0A
8
9
TMP19A44
D7A' D6A' D5A' D4A'
1
2
2010-04-01
3
4