tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 617

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TMP19A44
Writing to data cells is automatically performed by an internal sequencer and no external control
by the CPU is required. The state of automatic page programming (whether it is in writing
operation or not) can be checked by the FLCS [0] <FlashBusy> register.
Also, any new command sequence is not accepted while it is in the automatic page programming
mode. If it is desired to interrupt the automatic page programming, use the hardware reset function.
If the operation is stopped by a hardware reset operation, it is necessary to once erase the page and
then perform the automatic page programming again because writing to the page has not been
normally terminated.
The automatic page programming operation is allowed only once for a page already erased. No
programming can be performed twice or more times irrespective of the data cell value whether it is
"1" or "0." Note that rewriting to a page that has been once written requires execution of the
automatic block erase or automatic chip erase command before executing the automatic page
programming command again. Note that an attempt to rewrite a page two or more times without
erasing the content can cause damages to the device.
No automatic verify operation is performed internally to the device. So, be sure to read the data
programmed to confirm that it has been correctly written.
The automatic page programming operation starts when the fourth bus write cycle of the command
cycle is completed. On and after the fifth bus write cycle, data will be written sequentially starting
from the next address of the address specified in the fourth bus write cycle (in the fourth bus write
cycle, the page top address will be command written) (32 bits of data is input at a time). Be sure to
use the SW command in writing commands on and after the fourth bus cycle. In this, any SW
command shall not be placed across word boundary. On and after the fifth bus write cycle, data is
command written to the same page area. Even if it is desired to write the page only partially, it is
required to perform the automatic page programming for the entire page. In this case, the address
input for the fourth bus write cycle shall be set to the top address of the page. Be sure to perform
command write operation with the input data set to "1" for the data cells not to be set to "0." For
example, if the top address of a page is not to be written, set the input data of the fourth bus write
cycle to 0xFFFFFFFF to command write the data.
Once the fourth bus cycle is executed, it is in the automatic programming operation. This condition
can be checked by monitoring the register bit FLCS [0] <FlashBusy> (SeeTable 24.10). Any new
command sequence is not accepted while it is in automatic page programming mode. If it is desired
to stop operation, use the hardware reset function. Be careful in doing so because data cannot be
written normally if the operation is interrupted. When a single page has been command written
normally terminating the automatic page writing process, the FLCS [0] <FlashBusy> bit is set to
"1" and it returns to the read mode.
When multiple pages are to be written, it is necessary to execute the page programming command
for each page because the number of pages to be written by a single execution of the automatic
page program command is limited to only one page. It is not allowed for automatic page
programming to process input data across pages.
Data cannot be written to a protected block. When automatic programming is finished, it
automatically returns to the read mode. This condition can be checked by monitoring FLCS [0]
<FlashBusy> (See Table 24.10). If automatic programming has failed, the flash memory is locked
in the mode and will not return to the read mode. For returning to the read mode, it is necessary to
use the reset command or hardware reset to reset the flash memory or the device. In this case,
while writing to the address has failed, it is recommended not to use the device or not to use the
block that includes the failed address.
Flash Memory Operation
TMP19A44 (rev1.3)24-32
2010-04-01