tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 352

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.5 Up-and-down counter
13.6 Interrupt
•
The PHCNT0 interrupt is enabled using the interrupt controller (INTC). The PHCNT0 interrupt is generated by counting
up or down. Reading the status register PHCFLG during interrupt handling allows simultaneous check for occurrences of
an overflow and an underflow. If PHCnFLG<OVFn> is "1," it indicates that an overflow has occurred. If <UDFn> is "1,"
it indicates that an underflow has occurred. This register is cleared after “1” is written. The counter becomes 0x0000
when an overflow occurs, and it becomes 0xFFFF when an underflow occurs. After that, the counter continues the
counting operation.
•
The two-phase input pulse input counter operates. The PHCNT0 interrupt is generated by the count-up or count-down
input, and the system recovers from the SLEEP mode. Reading the status register PHCFLG during interrupt handling
allows simultaneous check for occurrences of an overflow, an underflow and a compare interrupt. This register is cleared
after “1” is written. The counter becomes 0x0000 when an overflow occurs, it and becomes 0xFFFF when an underflow
occurs. After that, the counter continues the counting operation.
Two-phase Pulse Input Counter (PHCNT)
When starting the two-phase input count (PHCRUN<PHCRUN> = "1"), the up-counter is initialized to 0x7FFF and
becomes ready for receiving counts. If a counter overflow occurs, the counter returns to 0x0000. If a counter
underflow occurs, the counter returns to 0xFFFF. After that, the counter continues the counting operation. Therefore,
the state can be checked by reading the counter value and the status flag PHCFLG after an interrupt is generated.
In the NORMAL or SLOW mode
In the SLEEP/ backup SLEEP mode
Up-count input
Up-and-down counter value
Up-and-down interrupt
(Note 1) The up (down) count input must be set to the "H" level for the states before and
(Note 2) Reading of counter value must be executed during PHCNT0 interrupt handling.
after an input.
0x3FFF
TMP19A44(rev1.3)13-12
0x4000
TMP19A44
0x4001
2010-05-10