tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 438

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Bus Interface (SBI)
SCL line
Internal SDA output
(Master A)
Internal SDA output
(Master B)
SDA line
16.5.8
16.5.9
16.5.10 Lost-arbitration Detection Monitor
When a serial bus interface interrupt request (INTS0) is generated, SBICR2 <PIN> is cleared to "0."
While <PIN> is "0," the SBI pulls the SCL line to the "L" level.
After transmission or reception of one data word, <PIN> is cleared to "0." It is set to "1" when data is
written to or read from SBIDBR. It takes a period of t
set to "1."
In the address recognition mode (<ALS> = "0"), <PIN> is cleared to "0" when the received slave
address matches the value specified at I2CAR or when a general-call address is received; i.e., the eight
bits following the start condition are all zeros. When the program writes "1" to SBICR2<PIN>, it is set
to "1." However, writing "0" does clear this bit to "0."
SBICR2 <SBIM1:0> selects an operating mode of the serial bus interface. <SBIM1:0> must be set to
"10" to configure the SBI for the I
operating mode to the port mode.
The I
bus arbitration procedure to ensure correct data transfer.
A master that attempts to generate the start condition while the bus is busy loses bus arbitration, with no
start condition occurring on the SDA and SCL lines. The I
line.
The arbitration procedure for two masters on a bus is shown below. Up until point a, Master A and
Master B output the same data. At point a, Master A outputs the "L" level and Master B outputs the "H"
level. Then Master A pulls the SDA bus line to the "L" level because the line has the wired-AND
connection. When the SCL line goes high at point b, the slave device reads the SDA line data, i.e., data
transmitted by Master A. At this time, data transmitted by Master B becomes invalid. In other words,
Master B loses arbitration. Master B releases its SDA pin, so that it does not affect the data transfer
initiated by another master. If two or more masters have transmitted exactly the same first data word,
the arbitration procedure continues with the second data word.
2
C bus has the multi-master capability (there are two or more masters on a bus), and requires the
Interrupt Service Request and Release
Serial Bus Interface Operating Modes
TMP19A44 (rev1.3) 16-14
Fig. 16.7 Lost Arbitration
2
C bus mode. Make sure that the bus is free before switching the
a
b
LOW
Loses arbitration and sets the
internal SDA output to "1."
for the SCL line to be released after <PIN> is
2
C-bus arbitration takes place on the SDA
TMP19A44
2010-04-01