tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 98

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
Status
(No.12)
6.6.2.2
Status Register
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Write “000”.
“0” is read.
CP3
availability
0:
Unavailabl
e
1: Available
Write “0”.
Undefine
CU3
R/W
R/W
IM7
KX
15
23
PX
31
R
7
R
0
0
0
d
Vector
address
for
Bootstrap
Exception
1: Set in
internal
ROM
0: Set in
(Note 4)
CP2
availability
0:
Unavailabl
e
1: Available
Write “0”.
“0” is read.
external
memory
Undefine
BEV
R/W
CU2
R/W
R/W
IM6
14
22
30
SX
6
R
0
0
1
d
TMP19A44(rev1.3) 6-48
“0” is read.
CP1
availability
0:
Unavailabl
e
1: Available
Write “1” for
using FPU.
Undefine
R/W
CU1
R/W
IM5
UX
13
21
29
TS
R
5
R
0
0
0
d
1:
mode
Write “0”.
CP0
availability
0:
Unavailabl
e
1: Available
(Note 6)
Operating
Mode:
0: Kernel
mode
Interrupt Mask: (for hardware
interrupt)
Write ”111”.
Undefine
R/W
CU0
R/W
R/W
IM4
UM
12
20
SR
28
4
R
0
0
0
d
User
“0” is read.
NMI
interrupt
1:
Generated
0:
generated
(Note 5)
Low-power
consumptio
n mode
0: Halt
1: Doze
Specifies
core mode
in
mode.
R/W
R/W
R/W
NMI
IM3
11
19
27
RP
3
R
0
0
0
0
IDLE
Not
Set when
a Reset or
NMI
exception
is taken.
(Note 1)
“0” is read.
“0” is read.
Error
Level:
R/W
ERL
R/W
IM2
10
18
26
FR
2
R
R
1
0
0
0
TMP19A44
taken.
(Note 2)
Exception
Level:
Set when
an
exception
other than
Reset and
NMI
exception
s is
Interrupt Mask: (for
software interrupt)
Write ”1”.
“0” is read. “0” is read.
EXL
R/W
R/W
IM1
17
25
RE
1
9
R
0
0
0
0
Impl
2010-04-01
R
1:
Interrupts
are
enabled.
(Note 3)
Interrupt
Enable:
0:
Interrupts
are
disabled.
R/W
R/W
IM0
16
24
MX
IE
0
8
R
0
0
0
0