tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 81

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
Returning to preceding
6.5.2.2
Execute exception
handler program
Processing
program
Preparation
unexpected interrupt on the way.
Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then enable the interrupt
by the CPU.
unexpected interrupt. First, configure the precondition. Secondly, clear the data related to the interrupt in the
clock generator and INTC, and then enable the interrupt.
When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any
Initiating an interrupt or changing its configuration must be implemented in the following order basically.
To configure the clock generator and INTC, you must follow the order indicated here not to cause any
The following sections are listed in the order of interrupt handling and describe how to configure them.
(1) Disabling interrupt by CPU
(2) CPU registers setting
(3) Preconfiguration 1 (Interrupt from external pin)
(4) Preconfiguration 2 (interrupt from peripheral IP)
(5) Preconfiguration 3 (software)
(6) Configuring the clock generator (standby clear factor only)
(7) Configuring INTC
(8) Enabling interrupt by CPU
Program for the exception handler.
Clear the interrupt factor if needed.
Configure to return to the preceding program from the
exception handler.
TMP19A44(rev1.3) 6-31
Details
TMP19A44
2010-04-01
Exception
handler
6.5.2.7
See