tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 484

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Watchdog Timer
18.3 Control Registers
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
18.3.1
18.3.2
This is a register for disabling the watchdog timer function and controlling the clearing function of the
binary counter.
(Note)
• Disabling control
• Enabling control
• Watchdog timer clearing control
Specifying the detection time of the watchdog timer <WDTP1: 0>
This is a 2-bit register for specifying the watchdog timer interrupt time for runaway detection.
When a reset is effected, this register is initialized to WDMOD <WDTP1, 0> = "00." Fig. 18.4
shows the detection time of the watchdog timer.
Enabling/disabling the watchdog timer <WDTE>
When reset, WDMOD <WDTE> is initialized to "1" and the watchdog timer is enabled.
To disable the watchdog timer, this bit must be set to "0" and, at the same time, the disable code
(B1H) must be written to the WDCR register. This dual setting is intended to minimize the
probability that the watchdog timer may inadvertently be disabled if a runaway occurs.
To change the status of the watchdog timer from "disable" to "enable," set the <WDTE> bit to "1."
Watchdog timer out reset connection <RESCR>
This is a register for specifying whether or not to reset the watchdog timer itself after a runaway is
detected. As a reset initializes this setting to WDMOD <RESCR>="0," a reset initiated the output
of the watchdog timer is not performed.
By writing the disable code (B1H) to this WDCR register after setting WDMOD <WDTE> to "0,"
the watchdog timer can be disabled.
Set WDMOD <WDTE> to "1."
Writing the clear code (4EH) to the WDCR register clears the binary counter and allows it to
resume counting.
Watchdog Timer Mode Register (WDMOD)
Watchdog Timer Control Register (WDCR)
(Runaway Detection Timer)
WDMOD
WDCR
WDCR
Writing the disable code (BIH) clears the binary counter.
← 0
← 1 0 1 1 0 0 0 1
← 0 1 0 0 1 1 1 0
− − − − − − −
TMP19A44(rev0.3) 18-3
Clears WDTE to "0."
Writes the disable code (B1H).
Writes the clear code (4EH)
TMP19A44
2010-04-01