tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 458

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Bus Interface (SBI)
<SIOS>
<SIOF>
<SEF>
SCK pin (output)
SI pin
INTS0 interrupt request
SBIDBR
(Note)
8-bit transmit/receive mode
Set the control register to the transfer/receive mode. Then writing the transmit data to SBIDBR
and setting SBICR1 <SIOS> to "1" enables transmission and reception. The transmit data is output
through the SO pin at the falling of the serial clock, and the received data is taken in through the SI
pin at the rising of the serial clock, with the least-significant bit (LSB) first. Once the shift register
is loaded with the 8-bit data, it transfers the received data to SBIDBR and the INTS0 interrupt
request is generated. The interrupt service program reads the received data from the data buffer
register and writes the next transmit data. Because SBIDBR is shared between transmit and
receive operations, the received data must be read before the next transmit data is written.
In the internal clock operation, the serial clock will be automatically in the wait state until the
received data is read and the next transmit data is written.
In the external clock mode, shift operations are executed in synchronization with the external serial
clock. Therefore, the received data must be read and the next transmit data must be written before
the next shift operation is started. The maximum data transfer rate for the external clock operation
varies depending on the maximum latency between generating the interrupt request and reading the
received data and writing the transmit data.
At the beginning of transmission, the same value as in the last bit of the previously transmitted data
is output in a period from setting <SIOF> to "1" to the falling edge of SCK.
Transmission and reception can be terminated by clearing <SIOS> to "0" or setting SBICR1
<SIOINH> to "1" in the INTS0 interrupt service program. If <SIOS> is cleared, transmission and
reception continue until the received data is fully transferred to SBIDBR. The program checks
SBISR <SIOF> to determine whether transmission and reception have come to an end. <SIOF> is
cleared to "0" at the end of transmission and reception. If <SIOINH> is set, the transmission and
reception are aborted immediately and <SIOF> is cleared to "0."
The contents of SBIDBR will not be retained after the transfer mode is
changed. The ongoing transmission and reception must be completed by
clearing <SIOS> to "0" and the last received data must be read before the
transfer mode is changed.
Fig. 16.20 Receive Mode (Example: Internal Clock)
a
0
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1
TMP19A44 (rev1.3) 16-34
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2
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5
Read the received data
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7
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0
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<SIOS> is cleared
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TMP19A44
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Read the received data
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2010-04-01
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