tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 393

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (HSIO)
HRXD0
(shares P91)
HSCLK0
output
(shares P92)
15.2 Block Diagram (Channel 0)
f
SYS/2
Fig. 15.2 shows the block diagram of HSIO0.
Each channel consists of a prescaler, a serial clock generation circuit, a receive buffer and its control circuit, and
a send buffer and its control circuit. Each channel functions independently.
f
SYS
HSC0MOD0
<RXE>
FIFO control
RB8
I/O interface mode
Serial clock generation circuit
RXDCLK
Receive buffer 1 (shift register)
Receive counter
Receive buffer 2 (HSC0BUF)
(Φ16 only with
Internal data bus
<BR0S5 : 0>
Receive
UART)
control
HBR0CR
Baud rate
generator
<BR0ADDE>
HBR0CR
Fig. 15.2 HSIO0 Block Diagram
HSC0MOD0
<WU>
<OERR><PERR><FERR>
<BR0K3 : 0>
HBR0ADD
TMP19A44(rev1.3) 15-3
<PE>
Parity control
HSC0CR
Error flag
÷ 2
HSC0CR
interrupt control
<EVEN>
(from TMRB3)
channel
Serial
TB8OUT
HSC0MOD0
HSC0CR
<SC1, 0>
Internal data bus
<IOC>
I/O interface mode
UART
Mode
HSC0MOD0
HTXDCLK
<SM1, 0>
TB8
Send buffer 1 (shift register)
Transmit counter
(Φ16 only with
Send buffer 2 (HSC0BUF)
Internal data bus
UART)
Transmit
HSIOCLK
control
FIFO control
HSC0MOD0
TMP19A44
<CTSE>
Interrupt request
HINTRX0
Interrupt request
HINTTX0
2010-04-01
HCTS0
(shares P92)
HTXD0
(shares P90)