tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 17

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Pin Layout and Pin Functions
2.3
P00~P07
D0~D7
AD0~D7
P10~P17
D8~D15
AD8~AD15
A8~A15
P20~P27
A16~A23
A0~A7
TB1IN0,TB1IN1
TB2IN0,TB2IN1
TB3IN0,TB3IN1
TB5IN0,TB5IN1
P30
P31
P32
TC0IN
P33
RDY
P34
TBEOUT
P35
TC1IN
P36
TC2IN
P37
ALE
TC3IN
RD
HWR
BUSRQ
BUSAK
R
WR
WAIT
Pin name
/
W
Pin Names and Functions
Table 2-2 through Table 2-9 show the names and functions of input and output pins.
No. of
8
8
8
1
1
1
1
1
1
1
1
pins
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
O
O
I
I
I
I
I/O
O
I/O
O
I/O
O
I
I/O
I
I
I/O
I
O
I/O
O
I
I/O
O
I
I/O
O
I
output
Input/
Table 2-2 Pin names and functions (1/8)
Port 30: Port used exclusively for output
Bus request: Signal requesting CPU to allow an external master
to take the bus control authority
Address latch enable (address latch is enabled only if access to
external memory (multiplexed bus mode) is taking place).
Port 0: Input/output port that allows input/output to be set in
units of bits
Data (lower): Data bus 0 to 7 (separate bus mode)
Address data (lower): Address data bus 0 to 7 (multiplexed bus
mode)
Port 1: Input/output port that allows input/output to be set in
units of bits
Data (upper): Data bus 8 to 15 (separate bus mode)
Address data (upper): Address data bus 8 to 15 (multiplexed
bus mode)
Address: Address bus 8 to 15 (multiplexed bus mode)
Port 2: Input/output port that allows input/output to be set in
units of bits
Address: Address bus 15 to 23 (separate bus mode)
Address: Address bus 0 to 7 (multiplexed bus mode)
16-bit timer 1 input 0,1: For inputting the count/capture trigger
of a 16-bit timer 1
16-bit timer 2 input 0,1: For inputting the count/capture trigger
of a 16-bit timer 2
16-bit timer 3 input 0,1: For inputting the count/capture trigger
of a 16-bit timer 3
16-bit timer 5 input 0,1: For inputting the count/capture trigger
of a 16-bit timer 5
RD Output Read: Strobe signal for reading external memory
Port 31: Port used exclusively for output
Write: Strobe signal for writing data of D0 to D7 pins
Port 32: Input/output port
Write upper-pin data: Strobe signal for writing data of D8 to
D15 pins
For inputting the capture trigger for 32-bit timer
Port 33: Input/output port
Wait: Pin for requesting CPU to put a bus in a wait state
Ready: Pin for notifying CPU that a bus is ready
Port 34: Input/output port
16-bit timer E output: Pin for outputting 16-bit timer E
Port 35: Input/output port
For inputting the capture trigger for 32-bit timer
Port 36: Input/output port
Read/write: "1" shows a read cycle or a dummy cycle. "0"
shows a write cycle.
For inputting the capture trigger for 32-bit timer
Port 37: Input/output port
For inputting the capture trigger for 32-bit timer
Bus acknowledge: Signal notifying that CPU has released the
bus control authority in response to BUSRQ
TMP19A44 (rev1.3) 2-3
Function
TMP19A44
Programma
ble Pull up/
Pull down
P-up
P-up
P-up
P-up
P-up
P-up
P-up
P-up
P-up
P-up
P-up
2010-04-01
Schmitt
trigger
Programma
ble Open
Output
Drain