tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 313

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TBnST
(0xFF00_4xxC)
TBnIM
(0xFF00_4xx0)
<INTTBn0>: Interrupt generated if there is a match with timer register 0 (TBnRG0)
<INTTBn1>: Interrupt generated if there is a match with timer register 1 (TBnRG1)
<INTTB0Fn>: Interrupt generated if an up-counter overflow occurs
(Note)
the generation of interrupt is notified to INTC. The flag is cleared by reading the TBnST register.
＜TBIMn0＞:Interrupt is masked if there is a match with timer register 0 (TBnRG0).
＜TBIMn1＞:Interrupt is masked if there is a match with timer register 1 (TBnRG1).
＜TBIMOFn＞:Interrupt is masked if an up-and-down counter overflow occurs.
16-bit Timer/Event Counters (TMRBs)
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
If any interrupt is generated, the flag that corresponds to the interrupt is set to TBnST and
Function
Function
15
23
31
15
23
31
7
7
14
22
30
14
22
30
TMRBn Interrupt Mask Register (n=0~11)
This can be read as “0”.
This can be read as “0”.
6
6
TMRBn Status Register (n=0~11)
TMP19A44(rev1.3) 11-15
13
21
29
13
21
29
R
R
5
0
5
0
12
20
28
12
20
28
4
4
R
R
R
R
R
R
0
0
0
0
0
0
11
19
27
11
19
27
3
3
1: Interrupt
1:
0: Interrupt
generated
INTTBOFn
TBIMOFn
generated
Interrupt
is
masked
not
10
18
26
10
18
26
2
0
2
0
1: Interrupt
1:
Interrupt
is
masked
INTTBn1 INTTBn0
0: Interrupt
generated
TBIMn1
generated
not
R/W
17
25
17
25
R
1
0
9
1
0
9
TMP19A44
1: Interrupt
1:
Interrupt
is
masked
0: Interrupt
generated
TBIMn0
generated
not
16
24
16
24
0
0
8
0
0
8
2010-04-01