tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 276

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
2 : 0
Bit
31
23
22
21
20
19
18
Mnemonic
BED
Conf
AbC
BES
Act
NC
⎯
⎯
Channel active
Normal completion
Abnormal completion
(Reserved)
Source bus error
Destination bus error
Configuration error
(Reserved)
Fig. 10.6 Channel Status Register (CSRn) (2 of 2)
Field name
TMP19A44 (rev1.3) 10-13
Channel Active (initial value: 0)
Indicates whether the channel is in a standby mode:
1: In a standby mode
0: Not in a standby mode
Normal Completion (initial value: 0)
Indicates normal completion of channel operation. If an interrupt
at normal completion is permitted by the CCR register, the
DMAC requests an interrupt when the NC bit becomes 1.
This setting can be cleared by writing 0 to the NC bit. If a request
for an interrupt at normal completion was previously issued, the
request is canceled if the NC bit becomes 0.
If an attempt is made to set the Str bit to 1 when the NC bit is 1,
an error occurs. To start the next transfer, the NC bit must be
cleared to 0. A write of 1 will be ignored.
1: Channel operation has been completed normally.
0: Channel operation has not been completed normally.
Abnormal Completion (initial value: 0)
Indicates abnormal completion of channel operation. If an
interrupt at abnormal completion is permitted by the CCR
register, the DMAC requests an interrupt when the AbC bit
becomes 1.
This setting can be cleared by writing 0 to the AbC bit. If a
request for an interrupt at abnormal completion was previously
issued, the request is canceled if the AbC bit becomes 0.
Additionally, if the AbC bit is cleared to 0, each of the BES, BED
and Conf bits are cleared to 0.
If an attempt is made to set the Str bit to 1 when the AbC bit is 1,
an error occurs. To start the next transfer, the AbC bit must be
cleared to 0. A write of 1 will be ignored.
1: Channel operation has been completed abnormally.
0: Channel operation has not been completed abnormally.
This is a reserved bit. Always set this bit to "0."
Source Bus Error (initial value: 0)
1: A bus error has occurred when the source was accessed.
0: A bus error has not occurred when the source was accessed.
Destination Bus Error (initial value: 0)
1: A bus error has occurred when the destination was accessed.
0: A bus error has not occurred when the destination was
accessed.
Configuration Error (initial value: 0)
1: A configuration error has occurred.
0: A configuration error has not occurred.
These three bits are reserved bits. Always set them to "0."
Description
TMP19A44
2010-04-01