tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 237

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

External Bus Interface
8.3 External Bus Operations (Separate Bus Mode)
This section describes various bus timing values. The timing diagram shown below assumes that the address
buses are A23 through A0 and that the data buses are D15 through D0.
(1) Basic bus operation
The external bus cycle of the TMP19A44 basically consists of three clock pulses and a wait can be inserted
as mentioned later. The basic clock of an external bus cycle is the same as the internal system clock.
Fig. 8.1 shows read bus timing and Fig. 8.2 shows write bus timing. If internal areas are accessed, address
buses remain unchanged as shown in these figures. Additionally, data buses are in a state of high impedance
and control signals such as RD and
CSn
A [23:0]
D [15:0]
CSn
A [23:0]
D [15:0]
RD
WR
Fig. 8.1 Read Operation Timing Diagram
Fig. 8.2 Write Operation Timing Diagram
TMP19A44 (rev1.3) 8-9
WR
External access
External access
do not become active.
tsys
tsys
DATA
DATA
Address HOLD
No output of RD
Internal access
Internal access
Output High − Z
No output of WR
Output High − Z
Address HOLD
TMP19A44
2010-04-01