xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 106

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

XRT94L33
Rev.1.2.0.
W6
W5
U6
U5
H5
E4
E5
RXCAPN_R
RXCAPP_R
REFSEL_L
RXCAPP
RXCAPN
TMS
TCK
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
I
I
I
I
I
I
I
ANAL0OG
ANALOG
ANALOG
ANALOG
TTL
TTL
TTL
F
M
ILTERING
ISCELLANEOUS
Test clock: Boundary Scan clock input
Note:
Test Mode Select: Boundary Scan Mode Select input
Note:
External Loop Capacitor for Receive PLL:
This pin connects to the positive side of the external capacitor,
which is used to minimize jitter peaking.
External Loop Capacitor for Receive PLL:
This pin connects to the negative side of the external capacitor,
which is used to minimize jitter peaking.
External Redundant Loop Capacitor for Receive PLL:
This pin connects to the positive side of the external capacitor,
which is used to minimize jitter peaking.
External Redundant Loop Capacitor for Receive PLL:
This pin connects to the negative side of the external capacitor,
which is used to minimize jitter peaking.
Clock Synthesizer Block Select:
This input pin permits the user to configure the “Transmit
SONET” circuitry (within the XRT94L33) to use either of the
following clock signals as its timing source.
Setting this input pin “HIGH” configures the “Transmit SONET”
circuitry within the XRT94L33 to use the “Clock Synthesizer”
block as its timing source. In this mode, the user can supply
either a 19.44MHz, 38.88MHz, 51.84MHz or 77.76MHz clock
signal to the REFTTL input pin.
Setting this input pin “LOW” by-passes the “Clock Synthesizer”
block. In this case, the user MUST supply a 19.44MHz clock
signal to the REFTTL input pin in order to insure proper
performance.
106
C
a.
b.
APACITORS
This input pin should be pulled “Low” for normal
This input pin should be pulled “Low” for normal
The “Directly-Applied” 19.44MHz clock signal, which is
applied to the REFTTL input pin (P1) or,
The output of the “Clock Synthesizer” block (within the
chip).
operation.
operation.
P
INS
xr