xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 449

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Note:
In Single-PHY Mode operation, the ATM Layer Processor is pumping data into and receiving data from only
one PHY-Layer device, as depicted below in Figure 114
Figure 114 Simple Illustration of Single - PHY Mode Operation
This section presents a detailed description of the Receive UTOPIA Interface block operating in the “Single-
PHY” Mode. A description of the Transmit UTOPIA Interface block operating in the “Single-PHY” Mode is
presented in Section _. Whenever the Receive UTOPIA Interface block has been configured to operate in the
Single-PHY Mode, and whenever the ATM Layer Processor wishes to read out one or a series of ATM cells
from the Receive UTOPIA Interface block, it must do the following.
1. Check the level of the RxUClav pin
If the RxUClav pin is “high” then the RxFIFO contains some ATM cell data that needs to be read by the ATM
Layer processor. In this case, the ATM Layer processor should begin to read the cell data from the Receive
UTOPIA Interface block. However, if the RxUClav pin is “low”, then the RxFIFO does not contain any cell
data, that can be read. In this case, the ATM Layer processor should wait until RxUClav toggles “high” before
attempting to read any more cell data from the “Receive UTOPIA Interface block”.
UTOPIA
Disable
Level 3
B
R/W
IT
1
7
This configuration setting does not apply to the Transmit UTOPIA Interface block. Therefore, the user will also
need to configure the Transmit UTOPIA Interface block into the Single-PHY Mode, as described in Section _.
Multi-PHY
Polling
Enable
B
R/W
Transceiver
IT
0
To/From
Optical
6
Back to
Enable
Polling
B
Back
R/W
IT
0
5
TxLData_p
TxLData_n
RxLData_p
RxLData_p
XRT95L34
Indication
Enable
Status
RxUData[15:0]
TxUData[15:0]
Direct
B
R/W
IT
0
RxUEnB*
TxUEnB*
4
RxUClav
RxUSoC
RxUPrty
TxUClav
TxUSoC
TxUPrty
RxUClk
TxUClk
Receive UTOPIA/POS-
PHY Data Bus Width
B
R/W
449
IT
1
3
B
R/W
IT
1
2
Rx FIFO Clock Signal
Tx FIFO Clock Signal
Rx Start of Cell Input
Rx Utopia Data Bus Parity
Tx Start of Cell Output
Tx Write Enable Output
Tx Utopia Data Bus Parity
RxFlow Control Input
Rx Read Output Enable Signal
TxFlow Control Input
Rx ATM Cell Data
Tx ATM Cell Data
(ATM Layer Device)
B
R/W
ATM Switch
IT
X
Cell Size[1:0]
1
B
R/W
IT
X
0
XRT94L33
Rev.1.2.0.