xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 8

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

XRT94L33
Rev.1.2.0.
AD18
P
IN
#
S
IGNAL
PRDY_L/
DTACK*
RDY
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
N
AME
I/O
O
S
CMOS
T
IGNAL
YPE
READY or DTACK Output:
The exact function of this input pin depends upon wich mode the
Microprocessor Interface has been configured to operate in, as
described below.
Intel Asynchronous Mode – RDY* - READY output:
If the Microprocessor Interface has been configured to operate in
the Intel-Asyncrhronous Mode, then this output pin will function
as the “active-low” READY output.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic “low” level ONLY
when it (the Microprocessor Interface) is ready to complete or
terminate the current READ or WRITE cycle.
Microprocessor has determined that this input pin has toggled to
the logic “low” level, then it is now safe for it to move on and
execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface
block is holding this output pin at a logic “high” level, then the
MIcroprocessor is expected to extend this READ or WRITE
cycle, until it detect this output pin being toggled to the logic low
level.
Motorola Mode – DTACK* - Data Transfer Acknowledge
Output:
If the Microprocessor Interface has been configured to operate in
the Motorola-Asynchronous Mode, then this output pin will
function as the “active-low” DTACK* ouytput.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic low level, ONLY when
it (the Microprocessor Interface) is ready to complete or
terminate the current READ or WRITE cycle.
Microprocessor has determined that this input pin has toggled to
the logic “low” leve, then it is now safe for it to move on and
execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface
block is holding this output pin at a logic “high” level, then the
MIcroprocessor is expected to extend this READ or WRITE
cycle, until it detects this output pin being toggled to the logic low
level.
PowerPC 403 Mode – RDY – Ready Output:
If the Microprocessor Interface has been configured to operate in
the PowerPC 403 Mode, then this output pin will function as the
“active-high” READY output.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic high level, ONLY
when it (the Microprocessor Interface) is ready to complete or
terminate the current READ or WRITE cycle.
Microprocessor has sampled this signal being at a logic “high”
level (upon the rising edge of PCLK) then it is now safe for it to
move on and execute the next READ or WRITE cycle.
The Microprocessor Interface will update the state of this output
pin upon the rising edge of PCLK.
8
D
ESCRIPTION
xr
Once the
Once the
Once the