xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 359

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
The Receive STS-3 TOH Processor block will increment these registers either by the number of erred STS-3
frames detected, or by the number of B1 bits that are detected to be in error (within a given STS-3 frame),
depending upon user selection, as described below.
2.3.1.11.1
The user can configure the Receive STS-3 TOH Processor block to increment the “Receive STS-3 Transport
B1 Byte Error Count” Register, by the value “1” for each STS-3 frame that it determines to have at least one
bit-error within the B1 byte.
The user can accomplish this by setting Bit 0 (B1 Byte Error Type), within the “Receive STS-3 Transport
Control Register – Byte 0” to “1”, as illustrated below.
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
2.3.1.11.2
The user can configure the Receive STS-3 TOH Processor block to increment the “Receive STS-3 Transport
B1 Error Count” register by the number of B1 bits, which are determined to be in error. Therefore, in this
mode, it is possible for the Receive STS-3 TOH Processor block to increment this register by as much as the
value of “8” per STS-3 frame.
The user can accomplish this by setting Bit 0 (B1 Byte Error Type) within the “Receive STS-3 Transport
Control Register – Byte 0” to “0”, as illustrated below.
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
2.3.1.11.3
2.3.1.12
The Receive STS-3 TOH Processor Block has the responsibility for computing and verifying the Line BIP-8
(e.g., B2) byte within each incoming STS-3 frame. When the Receive STS-3 TOH Processor block executes
this function, it will do the following.
•
•
Unused
Unused
B
B
R/O
R/O
It will read in the contents of a given “newly received” STS-3 frame.
It will compute the BIP-8 value over the LOH (Line Overhead) and the Envelope Capacity, within this
STS-3 frame.
IT
IT
0
0
7
7
o
LINE BIP-8 (B2) BYTE VERIFICATION
Configuring the Receive STS-3 TOH Processor block to increment the “Receive STS-3
Transport B1 Byte Error Count” Registers on a “per-Frame” basis.
Configuring the Receive STS-3 TOH Processor block to increment the “Receive STS-3
Transport B1 Error Count” register on a “per B1 bit error” basis.
SF Detect
SF Detect
B1 Byte Performance Monitoring
It will increment the “Receive STS-3 Transport B1 Byte Error Count” registers. The “Receive
STS-3 Transport B1 Error Count” register is actually a 32 bit register that resides at Address
Locations = 0x1110 through 0x1113.
Enable
Enable
B
R/W
B
R/W
IT
0
IT
0
6
6
SD Detect
SD Detect
Enable
Enable
B
R/W
B
R/W
IT
0
IT
0
5
5
Descramble
Descramble
Disable
Disable
B
B
R/W
R/W
IT
0
IT
0
4
4
359
SDH/SONET*
SDH/SONET*
B
B
R/W
R/W
IT
IT
0
0
3
3
REI-L Error
REI-L Error
B
Type
B
Type
R/W
R/W
IT
IT
0
0
2
2
Error Type
Error Type
B2 Byte
B2 Byte
B
B
R/W
R/W
IT
IT
0
0
1
1
XRT94L33
Error Type
Error Type
B1 Byte
B1 Byte
Rev.1.2.0.
B
B
R/W
R/W
IT
IT
1
0
0
0