xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 158

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

XRT94L33
Rev.1.2.0.
Transmit UTOPIA Control Register – Byte 0, Address = 0x0583
Note:
In Single-PHY Mode operation, the ATM layer processor is pumping data into and receiving data from only
one PHY-Layer device, as depicted below in Figure 22.
Figure 12 Simple Illustration of Single - PHY Mode Operation
This section presents a detailed description of the Transmit UTOPIA Interface block operating in the “Single-
PHY” mode. A description of the Receive UTOPIA Interface block operating in the “Single-PHY” mode is
presented in Section _. Whenever the Transmit UTOPIA Interface block has been configured to operate in
the Single-PHY Mode, and whenever the ATM Layer Processor wishes to write one or a series of ATM cells
to the Transmit UTOPIA Interface block, it must do the following.
1. Check the level of the TxUClav output pin upon each rising edge of TxUClk.
If the TxUClav output pin is at a logic “high” then there is available space in the Tx FIFO for more ATM cell
data and the ATM Layer Processor may begin writing cell data to the Transmit UTOPIA Interface block.
However, if the TxUClav pin is “low”, then the Tx FIFO is too full to accept anymore data and the ATM Layer
Processor must wait until TxUClav toggles “high” before writing any cell data to the Transmit UTOPIA
Interface block.
2. Apply the first byte (or word) of the new cell to the Transmit UTOPIA Data Bus.
The ATM Layer processor must designate this byte (or word) as the beginning of a new cell, by pulsing the
TxUSoC input pin “high” for one period of TxUClk.
UTOPIA
Level
B
R/W
IT
1
7
This configuration setting does not apply to the Receive UTOPIA Interface block. Therefore the user will also
need to configure the Receive UTOPIA Interface block into the Single-PHY Mode, as described in Section _.
Transceiver
To/From
Optical
Multi-PHY
Mode
B
R/W
IT
0
6
TxLData_p
TxLData_n
RxLData_p
RxLData_p
Back Polling
Back-to-
Enable
B
R/W
XRT95L34
IT
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
RxUData[15:0]
TxUData[15:0]
RxUEnB*
TxUEnB*
RxUClav
RxUSoC
RxUPrty
TxUClav
TxUSoC
TxUPrty
RxUClk
TxUClk
Access
Status
Direct
B
R/W
IT
0
4
158
B
Data Bus Width[1:0]
R/W
Transmit UTOPIA
IT
1
3
Rx FIFO Clock Signal
Tx FIFO Clock Signal
RxFlow Control Input
Rx Start of Cell Input
Rx Utopia Data Bus Parity
Tx Start of Cell Output
Tx Write Enable Output
Tx Utopia Data Bus Parity
Rx Read Output Enable Signal
TxFlow Control Input
Rx ATM Cell Data
Tx ATM Cell Data
B
R/W
IT
1
2
(ATM Layer Device)
ATM Switch
B
R/W
Cell_Size_Sel[1:0]
IT
X
1
xr
B
R/W
IT
X
0