xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 315

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Transmit STS-3 Transport – Transmit J0 Byte Control Register (Direct Address = 0xN84F)
This step configures the “Transmit STS-3 TOH Processor” block to read out the contents of the “Transmit
Transport – Transmit J0 Byte Value” register; and load this value into the “J0 byte-field” within each outbound
STS-3 Frame.
STEP 2 – Write the desired byte value (for the “outbound” J0 byte) into the “Transmit STS-3 Transport
– Transmit J0 Byte Value” register.
The bit-format of this register is presented below.
Transmit STS-3 Transport – Transmitter J0 Value Register (Address = 0x194B)
2.2.9.5.5.4
The Transmit STS-3 TOH Processor block permits the user to source the contents of the J0 byte via the
“TxTOH_n” input port. The user can configure the Transmit STS-3 TOH Processor block to support this
feature by performing the following steps.
STEP 1 – Write the value “[1, 1]” into Bits 1 and 0 (J0 Type[1:0]) within the “Transmit STS-3 Transport
– Transmit J0 Byte Control” Register; as depicted below.
Transmit STS-3 Transport – Transmit J0 Control Register (Address = 0x194F)
This step configures the “Transmit STS-3 TOH Processor” block to accept the value of the J0 byte, via the
“TxTOH” input port and load this value into the J0 byte position within each outbound STS-3 frame.
STEP 2 – Begin providing the values of the “outbound” J0 Byte message to the “TxTOH” input port.
The procedure for applying the J0 byte to the “TxTOH” input port is presented below.
Using the “TxTOH” Input Port to insert the J0 byte value into the outbound STS-3 frame
If the user intends to externally insert the J0 byte into the outbound STS-3 frame, the “TxTOH” input port, then
they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD solution) to do
the following.
• Continuously sample the “TxTOHEnable_n” and the “TxTOHFrame_n” output pins upon the rising edge of
the “TxTOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxTOH Input Port” is presented below in
Figure 66.
B
B
B
R/W
R/O
R/O
IT
IT
IT
X
0
0
7
7
7
Setting and Controlling the “Outbound” J0 Byte via External Input pin
B
B
B
R/W
R/O
R/O
IT
IT
X
IT
0
0
6
6
6
Unused
Unused
B
B
B
R/W
R/O
R/O
IT
IT
IT
X
0
0
5
5
5
Transmit_J0_Byte[7:0]
B
B
B
R/W
R/O
R/O
IT
IT
IT
0
X
0
4
4
4
315
J0 Message Length[1:0]
J0 Message Length[1:0]
B
B
B
R/W
R/W
R/W
IT
IT
IT
X
X
X
3
3
3
B
B
B
R/W
R/W
R/W
IT
IT
IT
X
X
X
2
2
2
B
B
B
R/W
R/W
R/W
IT
IT
IT
X
1
1
1
1
1
J0 Type[1:0]
J0 Type[1:0]
XRT94L33
Rev.1.2.0.
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
X
1
0
0
0