xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 426

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

XRT94L33
Rev.1.2.0.
Receive ATM Cell Processor – Interrupt Enable Register (Address = 0xN70F)
Once the “Cell Extraction Buffer” receives a “COPIED” cell from the “Receive User Cell Filter”, then the
XRT94L33 will do all of the following:
• It will toggle the “INT*” output pin “LOW”.
• It will set Bit 5 (Cell Extraction Interrupt Status) within the Receive ATM Cell Processor – Interrupt Status
Register, to “1” as depicted below.
Receive ATM Cell Processor – Interrupt Status Register (Address = 0xN70B)
At this point, the user can now proceed onto STEP 3.
STEP 3 – Read out the very first 32-bit word of this new ATM cell from the “Receive Cell Extraction
Buffer”.
This is accomplished by executing the following four sub-steps.
STEP 3a – Read the contents of the first byte (of this newly received ATM cell) from the “Receive ATM
Cell – Insertion/Extraction Memory Register – Byte 3; as depicted below.
B
B
R/O
R/O
IT
IT
0
0
7
7
Unused
Unused
B
B
R/O
R/O
IT
IT
0
0
6
6
Extraction
Extraction
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
1
1
5
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Insertion
Insertion
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
0
0
4
4
426
Extraction
Extraction
Overflow
Overflow
Interrupt
Interrupt
Memory
Memory
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
0
0
3
3
Cell Insertion
Cell Insertion
Overflow
Overflow
Interrupt
Interrupt
Memory
Memory
Enable
Status
B
B
RUR
R/W
IT
IT
0
0
2
2
Detection of
Detection of
HEC Byte
HEC Byte
Interrupt
Interrupt
Enable
Status
B
Error
B
Error
RUR
R/W
IT
IT
0
0
1
1
xr
Detection of
Detection of
Parity Error
Parity Error
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
IT
IT
0
0
0
0