xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 321
xrt94l33
Manufacturer Part Number
xrt94l33
Description
Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
Manufacturer
Exar Corporation
Datasheet
1.XRT94L33.pdf
(465 pages)
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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Note:
•
“TxPOHEnable_n” pin “low”, then it should enter a “WAIT STATE” (e.g., where it waits for __ periods of
“TxPOHClk_n” to elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the
very first bit (e.g., the most significant bit) of the “outbound” F1 byte onto the “TxPOH_n” input pin, upon the
very next falling edge of “TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit STS-3c
POH Processor” block circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the F1 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
Figure 71 presents an illustration of the “TxPOH Input Interface” waveforms, when the “external circuit” is
writing the F1 byte into the “TxPOH Input Port”.
Figure 71 Illustration of the “TxPOH Input Interface” waveforms, when the “External Circuit” is writing
the “F1 byte” into the “TxPOH Input Port”
Whenever the “external circuit” samples the “TxPOHFrame_n” output pin “high” and also the
The “TxPOHIns_n” line (in Figure 70) is “dashed” because this controlling this signal is not necessary if the user
This “WAIT STATE” period is necessary because the F1 byte is the _ byte within the TOH.
has executed “STEP 2” above
XRT94L43 Device
TxPOHEnable_n
TxPOHFrame_n
TxPOHClk_n
TxPOHIns_n
TxPOH_n
321
TxPOHData_OUT
TxPOHFrame_IN
TxPOHEnable_IN
TxPOH_INSERT
TxPOHClk_IN
External Circuit
XRT94L33
Rev.1.2.0.
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