xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 176

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

XRT94L33
Rev.1.2.0.
Transmit ATM Control – Byte 0 Register (Address = 0xNF03)
Setting this bit-field to “1” configures the Transmit Cell Processor block to check and verify “ODD” Parity.
Conversely, setting this bit-field to “0” configures the Transmit Cell Processor block to check and verify
“EVEN” parity.
Note:
2.2.5.4
The Transmit ATM Cell Processor block permits the user to configure it to discard all cells that contain Parity
errors. The user can implement this selection by writing the appropriate value into Bit 4 (Discard Cell upon
Parity Error) within the “Transmit ATM Control – Byte 0” Register; as depicted below.
Transmit ATM Control – Byte 0 Register (Address = 0xNF03)
Setting this bit-field to “1’ configures the Transmit ATM Cell Processor block to discard all cells that contain
parity errors. Conversely, setting this bit-field to “0” configures the Transmit ATM Cell Processor block to
retain all cells (even if they contain parity errors).
Note:
2.2.5.5
The Transmit ATM Cell Processor block can be configured to generate an interrupt, anytime it detects a parity
error, within a given cell. The user can accomplish this by setting Bit 0 (Detection of Parity Error Interrupt
Enable), within the Transmit ATM Cell Processor – Interrupt Enable Register to “1”; as depicted below.
HEC Byte
HEC Byte
Invert
Invert
B
B
R/W
R/W
IT
IT
0
0
7
7
This bit-field is ignored if Bit 5 (Parity Check Enable) is set to “0”.
This bit-field is ignored if Bit 5 (Parity Check Enable) is set to “0”.
C
E
I
NTERRUPTS
RRORS
ONFIGURING THE
HEC Byte
HEC Byte
Enable
Enable
Check
Check
B
B
R/W
R/W
IT
IT
0
0
6
6
D
UE TO
Parity Check
Parity Check
Enable
Enable
T
B
B
R/W
R/W
D
RANSMIT
IT
IT
1
1
ETECTION OF
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
ATM C
Discard Cell
Discard Cell
upon Parity
upon Parity
B
Error
B
Error
R/W
R/W
“T
IT
IT
X
0
RANSMIT
4
4
ELL
176
P
ROCESSOR BLOCK TO
Odd Parity
Odd Parity
UTOPIA I
B
B
R/W
R/W
IT
X
IT
X
3
3
NTERFACE
B
B
R/O
R/O
IT
IT
0
0
2
2
” P
D
Unused
Unused
ARITY
ISCARD
E
B
B
RRORS
R/O
R/O
C
IT
IT
0
0
ELLS UPON
1
1
xr
Cell Payload
Cell Payload
Scramble
Scramble
Enable
Enable
B
B
R/W
R/W
P
IT
IT
0
0
ARITY
0
0