xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 173

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

xr
XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
2.2.4
T
T
D
P
HE
RANSMIT
ATA
ATH
All ATM cells that successfully pass through “Parity Checking” and “User Cell Filtering” will be processed via
the “HEC Byte Calculation & Insertion” Block. In this case, the Transmit ATM Cell Processor block will
optionally compute and insert the HEC byte into the fifth octet position within each outbound ATM cell and,
optionally scrambles the cell payload bytes.
When the TxFIFO does not contain a full cell, the Transmit ATM Cell Processor block will then proceed to
read out the contents of the “Transmit Cell Insertion” Buffer. Once the “Transmit Cell Insertion” Buffer has
been depleted, then the “Idle Cell Generator” block will begin to generate and transmit “Idle Cells” via the
Transmit Data Path. Finally, the Transmit ATM Cell Processor is also equipped with a serial input port that
permits the user to externally insert the value of the GFC (Generic Flow Control) field for each outbound cell.
Figure 30 presents an illustration of the functional block diagram of the Transmit ATM Cell Processor block
and the associated external pins.
A detailed description of the Transmit ATM Cell Processor block is presented below.
2.2.4.1
F
D
T
ATM C
P
UNCTIONAL
ESCRIPTION OF THE
RANSMIT
ELL
ROCESSOR
This section presents an in-depth functional description of the Transmit ATM Cell Processor block.
Additionally, this section presents all of the configuration options associated with the Transmit ATM Cell
Processor block.
The Transmit ATM Cell Processor consists of the following functional blocks.
• Parity Checker Block
• Transmit User Cell Filter Block
• HEC Byte Calculation & Insertion Block
• The Transmit Cell Insertion Buffer/Processor
• The Transmit Cell Extraction Buffer/Processor
• Cell Payload Scrambler Block
• IDLE Cell Generator Block
• “Transmit GFC Nibble-field” serial input port
Figure 21 presents an illustration of the Functional Block Diagram of the Transmit ATM Cell Processor block;
with each of these “above-mentioned” functional blocks noted.
Each of these “sub-blocks” will be discussed in some detail below. However, before we get too much into the
detailed functional description of the Transmit ATM Cell Processor block; the user MUST note that the
Transmit ATM Cell Processor block will NOT even function unless the user enables the “Transmit ATM Cell
Processor” block for operation. The user can enable the Transmit ATM Cell Processor block by setting Bit 0
(Transmit ATM Cell Processor Enable), within the “Transmit ATM Cell Processor Block – Transmit ATM
Control Register – Byte 2” to “1” as depicted below.
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