xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 390

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

XRT94L33
Rev.1.2.0.
Configuring the Receive STS-3c POH Processor block to increment the “Receive STS-3c Path – REI-P
Error Count” Register on an “REI-P Value” basis.
The user can configure the Receive STS-3c TOH Processor block to increment the “Receive STS-3c Path –
REI-P Error Count” Register by the contents within the “REI-P” nibbles, within each incoming STS-3c SPE.
Therefore, in this mode, it is possible for the Receive STS-3c POH Processor block to increment this register
by as much as the value “8” per STS-3c SPE.
The user can accomplish this by setting Bit 1 (REI-P Error Type) within the “Receive STS-3c Path – Control
Register – Byte 0” to “0”, as illustrated below.
Receive STS-3c Path – Control Register – Byte 0 (Address = 0x1183)
2.3.2.3
Configuring the Receive STS-3c POH Processor block to increment the “Receive STS-3c Path – B3
Error Count” Register on a “per-SPE” basis.
The Receive STS-3c POH Processor block has the responsibility for computing and verifying the Path BIP-8
(e.g., B3) byte within each incoming STS-3c SPE. When the Receive STS-3c POH Processor block executes
this function, it will do the following.
• It will read in the contents of a given “newly received” STS-3c SPE.
• It will compute the BIP-8 value over the SPE.
• This resulting BIP-8 value will be compared with the contents of the B3 byte, within the very next STS-3c
SPE.
The user can configure the Receive STS-3c POH Processor block to increment the “Receive STS-3c Path –
B3 Error Count” Register, by the value “1” for each STS-3c SPE that it determined to have a bit-error.
The user can accomplish this by setting Bit 0 (B3 Error Type), within the “Receive STS-3c Path – Control
Register – Byte 0” to “1”, as illustrated below.
Receive STS-3c Path – Control Register – Byte 0 (Address = 0x1183)
Note:
If the Receive STS-3c POH Processor block detects any B3 byte errors, then it will do the following.
B
B
R/O
R/O
a. It will generate the “Detection of B3 Error” Interrupt, by toggling the “INT*” output pin “LOW” and by
IT
IT
0
0
7
7
This the user implements this setting, then the corresponding Transmit STS-3c POH Processor block will set the
setting Bit 7 (Detection of B3 Byte Error Interrupt Status) to “1” as indicated below.
REI-P nibble value (within the G1 byte) to the number of erred SPE that have been detected. In this case, the
maximum value that the REI-P nibble (within an STS-3c SPE) will contain will be “1”.
PATH BIP-8 (B3) BYTE VERIFICATION
B
B
R/O
R/O
IT
IT
0
0
6
6
Unused
Unused
B
B
R/O
R/O
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
B
B
R/O
R/O
IT
IT
0
0
4
4
390
Check Stuff
Check
B
B
Stuff
R/W
R/W
IT
IT
0
0
3
3
RDI-P Type
RDI-P
B
Type
B
R/W
R/W
IT
IT
0
0
2
2
REI-P Error
Error Type
REI-P
B
B
Type
R/W
R/W
IT
IT
0
0
1
1
xr
B3 Error
B3 Error
Type
Type
B
B
R/W
R/W
IT
IT
0
1
0
0