xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 214

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

XRT94L33
Rev.1.2.0.
STEP 1 – Write the value “1” into Bit 3 (Transmit ATM Cell Processor Block Interrupt Enable), within
the “Operation Block Interrupt Enable” Register – Byte 0” as depicted below.
Operation Block Interrupt Enable Register – Byte 0 (Address = 0x0017)
Note:
STEP 2 – Set Bit 3 (Cell Extraction Memory Overflow Interrupt Enable), within the “Transmit ATM Cell
Processor – Interrupt Enable Register” to “1” as depicted below.
Transmit ATM Cell Processor – Interrupt Enable Register (Address = 0xNF0F)
This step enables the “Transmit Cell Extraction Memory Overflow” Interrupt at the “Source-Level”. Once the
user executes this write operation, then the Transmit ATM Cell Processor block will generate an interrupt to
the Microprocessor anytime the “Transmit Cell Extraction Buffer” experiences an “overflow” condition.
Processor
ATM Cell
Interrupt
Receive
Enable
B
R/O
Block
B
R/W
IT
0
IT
0
7
7
Unused
This step enables the “Transmit ATM Cell Processor” block for Interrupt Generation, at the “Block Level”.
B
R/O
IT
Interrupt
Receive
0
Enable
STS-3
Block
B
TOH
6
R/W
IT
0
6
Extraction
Interrupt
Enable
B
R/W
Cell
POH Block
IT
0
SONET/
Interrupt
Receive
Enable
5
VC-3
B
R/W
IT
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
Insertion
Interrupt
Enable
B
R/W
Cell
Processor
Interrupt
IT
Receive
0
Enable
Block
B
PPP
R/W
4
IT
0
4
214
Extraction
Overflow
Interrupt
Memory
Enable
Processor
B
R/W
ATM Cell
Cell
Transmit
Interrupt
Enable
IT
1
Block
B
R/W
3
IT
1
3
Cell Insertion
Overflow
Interrupt
Memory
Enable
B
R/W
B
IT
0
R/O
IT
0
2
2
Unused
Detection of
HEC Byte
Interrupt
Enable
B
Error
R/W
B
R/O
IT
0
IT
0
1
1
xr
Detection of
Parity Error
Processor
Interrupt
Transmit
Interrupt
Enable
Enable
Block
B
B
R/W
PPP
R/W
IT
0
IT
0
0
0