xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 174

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

XRT94L33
Rev.1.2.0.
Transmit ATM Cell Processor Block – Transmit ATM Control Register – Byte 2 (Address = 0xNF01)
Figure 21: Functional Block Diagram of the Transmit ATM Cell Processor Block
2.2.5
Whenever the ATM Layer Processor writes ATM cell data into the Transmit UTOPIA Interface block; it will do
so by placing a sequence of bytes or (16-bit) words unto the Transmit UTOPIA Interface data bus
(TxUData[15:0]). As the ATM Layer Processor is placing each byte or word (or a given ATM cell); into the
Transmit UTOPIA Data bus, it is expected to compute the odd parity of each of these bytes or words.
Additionally, the ATM Layer Processor is expected to apply this parity value to the “TxUPrty” input pin,
coincident with placing the corresponding byte or word (of ATM cell data) onto the Transmit UTOPIA Data
Bus.
The Transmit UTOPIA Interface block will latch the contents of a given byte or word (of ATM cell data) upon
the rising edge of “TxUClk”. As the Transmit UTOPIA Interface block samples and latches each byte or word
B
R/O
IT
0
7
Transmit UTOPIA
T
HE
Interface Block
P
TxFIFO
TxFIFO
ARITY
B
R/O
Main Data Path
IT
0
6
C
HECKER
B
R/O
B
IT
0
LOCK
Generator
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Checker
5
Generator
Checker
Parity
Idle Cell
Block
Parity
Idle Cell
Block
Unused
B
R/O
IT
0
4
User Cell
Calculation
HEC Byte
User Cell
Calculation
Insertion
HEC Byte
Block
Filter
Insertion
Block
174
Filter
Block
Block
&
&
B
R/O
IT
0
3
Cell Extraction
Cell Insertion
Cell Extraction
Transmit GFC
Cell Insertion
Cell Payload
Processor
Processor
Transmit GFC
Nibble-Field
Cell Payload
Processor
Scrambler
Processor
Buffer/
Nibble-Field
Input Port
Buffer/
Scrambler
Buffer/
Input Port
Buffer/
Block
Block
Block
Block
B
R/O
IT
0
2
Microprocessor
Microprocessor
Processor Block
SONET/STS-3c
B
To Transmit
R/O
Interface
Input Port
Interface
IT
0
TxGFC
Block
Block
POH
1
xr
Processor
ATM Cell
Transmit
Enable
B
R/W
IT
1
0