HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 391

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

10.5.3 Interrupt Sources and DMA Controller Activation
Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input
capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all
independently vectored. An interrupt is requested when the interrupt request flag and interrupt
enable bit are both set to 1.
The priority order of the channels can be modified in interrupt priority registers A and B (IPRA
and IPRB). For details see section 5, Interrupt Controller.
Compare match/input capture A interrupts in channels 0 to 3 can activate the DMA controller
(DMAC). When the DMAC is activated a CPU interrupt is not requested.
Table 10-10 lists the interrupt sources.
Table 10-10 ITU Interrupt Sources
Channel
0
1
2
3
4
Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed
by settings in IPRA and IPRB.
Interrupt
Source
IMIA0
IMIB0
OVI0
IMIA1
IMIB1
OVI1
IMIA2
IMIB2
OVI2
IMIA3
IMIB3
OVI3
IMIA4
IMIB4
OVI4
Description
Compare match/input capture A0
Compare match/input capture B0
Overflow 0
Compare match/input capture A1
Compare match/input capture B1
Overflow 1
Compare match/input capture A2
Compare match/input capture B2
Overflow 2
Compare match/input capture A3
Compare match/input capture B3
Overflow 3
Compare match/input capture A4
Compare match/input capture B4
Overflow 4
379
DMAC
Activatable
Yes
No
No
Yes
No
No
Yes
No
No
Yes
No
No
No
No
No
Priority*
High
Low