HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 413

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

11.2.5 Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP
TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of
NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or
different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1
and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be
modified and are always read as 1.
Address H'FFA5
Address H'FFA7
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
7
to TP
NDR7
R/W
—
—
7
0
7
1
0
Next data 7 to 4
These bits store the next output
data for TPC output group 1
). During TPC output, when an ITU compare match event specified in
NDR6
R/W
—
—
6
0
6
1
NDR5
R/W
—
—
5
0
5
1
401
NDR4
R/W
Reserved bits
—
—
4
0
4
1
NDR3
R/W
—
—
3
0
3
1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
NDR2
R/W
—
—
2
0
2
1
NDR1
R/W
—
—
1
0
1
1
NDR0
R/W
—
—
0
0
0
1