MT90520AG ZARLINK [Zarlink Semiconductor Inc], MT90520AG Datasheet

no-image

MT90520AG

Manufacturer Part Number

MT90520AG

Description

8-Port Primary Rate Circuit Emulation AAL1 SAR

Manufacturer

ZARLINK [Zarlink Semiconductor Inc]

Datasheet

1.MT90520AG.pdf (180 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

H&T Electronics

H&T Electronics

Part Number:

MT90520AG

Quantity:

19

Current page: 1 of 180
Download datasheet (2Mb)

Features

•

•

•

•

•

•

•

•

•

UTOPIA

Interface

AAL1 Segmentation and Reassembly device

compliant with Circuit Emulation Services (CES)

standard (af-vtoa-0078.000)

Supports both Unstructured and Structured

Circuit Emulation of 8 independent DS1/E1/ST-

BUS interfaces

Supports AAL1 trunking, with up to 128 TDM

channels per VC (af-vtoa-0089.001)

Supports CAS transmission and reception in all

structured modes of operation

Supports simultaneous processing of up to 256

bidirectional Virtual Circuits

Supports mixed DS1/E1 operation

Supports mixed Unstructured and Structured CES

operation

Fully flexible DS0 assignment

Complete clock recovery solution provided on-

chip: Synchronous, Adaptive, or Synchronous

MT90520

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

OUTPUT

UTOPIA

UTOPIA

BLOCK

BLOCK

INPUT

Scan Logic

Boundary-

Interface

Copyright 2002-2004, Zarlink Semiconductor Inc. All Rights Reserved.

JTAG

(UDT, SDT,

RX SARs

Figure 1 - MT90520 Block Diagram

SAR

TX

Data)

VC Look-Up

Table

Zarlink Semiconductor Inc.

External Memory Controller

Segmentation / Reassembly

1

Memory

Memory

Local

Local

•

•

•

•

•

•

Circular Buffers

Residual Time Stamp (SRTS) via 8 independent

PLLs

Dual-mode (ATM-end or PHY-end) UTOPIA port

operates in Level 1 or Level 2 mode for

connection to external PHY or ATM devices with

UTOPIA clock rate up to 52 MHz

TDM bus provides 8 bidirectional serial streams

at 1.544, 2.048, or 4.096 MHz - compatible with

Generic (1.544 Mbps or 2.048 Mbps) and ST-

BUS (2.048 Mbps) interfaces

Supports master and slave TDM backplane bus

clock operation

Supports TDM and UTOPIA loopback functions

16-bit microprocessor port, configurable to

Motorola or Intel timing

Master clock rate of 66.0 MHz

16-bit Microprocessor

Microprocessor

Interface Logic

MT90520AG

Rx/Reassembly (X 8)

Tx/Segmentation (X 8)

Interface

PLL

Circuit Emulation AAL1 SAR

Management

Ordering Information

OUTPUT

BLOCK

Clock

BLOCK

INPUT

-40 to +85°C

TDM

External

Synchronous

SRAM (ZBT)

TDM

456 Pin Plastic BGA

8-Port Primary Rate

Clock Control

/Recovery

Interface

TDM Output

Interface

TDM Input

Interface

Data Sheet

MT90520

January 2004

Related parts for MT90520AG

Related keywords

MT90520AG datasheet
MT90520AG data sheet
MT90520AG pdf datasheet
MT90520AG component
MT90520AG part
MT90520AG distributor
MT90520AG RoHS
MT90520AG datasheet download